444 lines
8.0 KiB
C
444 lines
8.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2015 Google, Inc
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*/
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#ifndef _ASM_ARCH_DDR_RK3288_H
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#define _ASM_ARCH_DDR_RK3288_H
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struct rk3288_ddr_pctl {
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u32 scfg;
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u32 sctl;
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u32 stat;
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u32 intrstat;
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u32 reserved0[12];
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u32 mcmd;
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u32 powctl;
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u32 powstat;
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u32 cmdtstat;
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u32 tstaten;
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u32 reserved1[3];
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u32 mrrcfg0;
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u32 mrrstat0;
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u32 mrrstat1;
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u32 reserved2[4];
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u32 mcfg1;
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u32 mcfg;
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u32 ppcfg;
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u32 mstat;
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u32 lpddr2zqcfg;
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u32 reserved3;
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u32 dtupdes;
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u32 dtuna;
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u32 dtune;
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u32 dtuprd0;
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u32 dtuprd1;
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u32 dtuprd2;
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u32 dtuprd3;
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u32 dtuawdt;
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u32 reserved4[3];
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u32 togcnt1u;
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u32 tinit;
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u32 trsth;
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u32 togcnt100n;
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u32 trefi;
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u32 tmrd;
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u32 trfc;
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u32 trp;
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u32 trtw;
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u32 tal;
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u32 tcl;
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u32 tcwl;
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u32 tras;
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u32 trc;
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u32 trcd;
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u32 trrd;
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u32 trtp;
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u32 twr;
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u32 twtr;
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u32 texsr;
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u32 txp;
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u32 txpdll;
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u32 tzqcs;
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u32 tzqcsi;
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u32 tdqs;
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u32 tcksre;
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u32 tcksrx;
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u32 tcke;
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u32 tmod;
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u32 trstl;
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u32 tzqcl;
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u32 tmrr;
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u32 tckesr;
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u32 tdpd;
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u32 reserved5[14];
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u32 ecccfg;
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u32 ecctst;
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u32 eccclr;
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u32 ecclog;
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u32 reserved6[28];
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u32 dtuwactl;
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u32 dturactl;
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u32 dtucfg;
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u32 dtuectl;
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u32 dtuwd0;
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u32 dtuwd1;
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u32 dtuwd2;
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u32 dtuwd3;
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u32 dtuwdm;
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u32 dturd0;
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u32 dturd1;
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u32 dturd2;
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u32 dturd3;
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u32 dtulfsrwd;
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u32 dtulfsrrd;
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u32 dtueaf;
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u32 dfitctrldelay;
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u32 dfiodtcfg;
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u32 dfiodtcfg1;
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u32 dfiodtrankmap;
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u32 dfitphywrdata;
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u32 dfitphywrlat;
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u32 reserved7[2];
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u32 dfitrddataen;
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u32 dfitphyrdlat;
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u32 reserved8[2];
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u32 dfitphyupdtype0;
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u32 dfitphyupdtype1;
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u32 dfitphyupdtype2;
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u32 dfitphyupdtype3;
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u32 dfitctrlupdmin;
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u32 dfitctrlupdmax;
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u32 dfitctrlupddly;
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u32 reserved9;
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u32 dfiupdcfg;
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u32 dfitrefmski;
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u32 dfitctrlupdi;
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u32 reserved10[4];
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u32 dfitrcfg0;
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u32 dfitrstat0;
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u32 dfitrwrlvlen;
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u32 dfitrrdlvlen;
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u32 dfitrrdlvlgateen;
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u32 dfiststat0;
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u32 dfistcfg0;
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u32 dfistcfg1;
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u32 reserved11;
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u32 dfitdramclken;
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u32 dfitdramclkdis;
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u32 dfistcfg2;
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u32 dfistparclr;
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u32 dfistparlog;
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u32 reserved12[3];
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u32 dfilpcfg0;
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u32 reserved13[3];
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u32 dfitrwrlvlresp0;
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u32 dfitrwrlvlresp1;
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u32 dfitrwrlvlresp2;
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u32 dfitrrdlvlresp0;
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u32 dfitrrdlvlresp1;
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u32 dfitrrdlvlresp2;
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u32 dfitrwrlvldelay0;
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u32 dfitrwrlvldelay1;
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u32 dfitrwrlvldelay2;
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u32 dfitrrdlvldelay0;
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u32 dfitrrdlvldelay1;
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u32 dfitrrdlvldelay2;
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u32 dfitrrdlvlgatedelay0;
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u32 dfitrrdlvlgatedelay1;
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u32 dfitrrdlvlgatedelay2;
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u32 dfitrcmd;
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u32 reserved14[46];
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u32 ipvr;
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u32 iptr;
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};
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check_member(rk3288_ddr_pctl, iptr, 0x03fc);
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struct rk3288_ddr_publ_datx {
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u32 dxgcr;
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u32 dxgsr[2];
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u32 dxdllcr;
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u32 dxdqtr;
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u32 dxdqstr;
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u32 reserved[10];
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};
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struct rk3288_ddr_publ {
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u32 ridr;
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u32 pir;
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u32 pgcr;
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u32 pgsr;
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u32 dllgcr;
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u32 acdllcr;
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u32 ptr[3];
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u32 aciocr;
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u32 dxccr;
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u32 dsgcr;
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u32 dcr;
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u32 dtpr[3];
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u32 mr[4];
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u32 odtcr;
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u32 dtar;
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u32 dtdr[2];
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u32 reserved1[24];
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u32 dcuar;
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u32 dcudr;
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u32 dcurr;
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u32 dculr;
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u32 dcugcr;
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u32 dcutpr;
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u32 dcusr[2];
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u32 reserved2[8];
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u32 bist[17];
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u32 reserved3[15];
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u32 zq0cr[2];
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u32 zq0sr[2];
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u32 zq1cr[2];
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u32 zq1sr[2];
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u32 zq2cr[2];
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u32 zq2sr[2];
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u32 zq3cr[2];
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u32 zq3sr[2];
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struct rk3288_ddr_publ_datx datx8[4];
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};
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check_member(rk3288_ddr_publ, datx8[3].dxdqstr, 0x0294);
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struct rk3288_msch {
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u32 coreid;
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u32 revisionid;
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u32 ddrconf;
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u32 ddrtiming;
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u32 ddrmode;
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u32 readlatency;
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u32 reserved1[8];
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u32 activate;
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u32 devtodev;
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};
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check_member(rk3288_msch, devtodev, 0x003c);
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/* PCT_DFISTCFG0 */
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#define DFI_INIT_START (1 << 0)
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/* PCT_DFISTCFG1 */
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#define DFI_DRAM_CLK_SR_EN (1 << 0)
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#define DFI_DRAM_CLK_DPD_EN (1 << 1)
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/* PCT_DFISTCFG2 */
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#define DFI_PARITY_INTR_EN (1 << 0)
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#define DFI_PARITY_EN (1 << 1)
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/* PCT_DFILPCFG0 */
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#define TLP_RESP_TIME_SHIFT 16
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#define LP_SR_EN (1 << 8)
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#define LP_PD_EN (1 << 0)
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/* PCT_DFITCTRLDELAY */
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#define TCTRL_DELAY_TIME_SHIFT 0
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/* PCT_DFITPHYWRDATA */
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#define TPHY_WRDATA_TIME_SHIFT 0
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/* PCT_DFITPHYRDLAT */
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#define TPHY_RDLAT_TIME_SHIFT 0
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/* PCT_DFITDRAMCLKDIS */
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#define TDRAM_CLK_DIS_TIME_SHIFT 0
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/* PCT_DFITDRAMCLKEN */
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#define TDRAM_CLK_EN_TIME_SHIFT 0
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/* PCTL_DFIODTCFG */
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#define RANK0_ODT_WRITE_SEL (1 << 3)
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#define RANK1_ODT_WRITE_SEL (1 << 11)
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/* PCTL_DFIODTCFG1 */
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#define ODT_LEN_BL8_W_SHIFT 16
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/* PUBL_ACDLLCR */
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#define ACDLLCR_DLLDIS (1 << 31)
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#define ACDLLCR_DLLSRST (1 << 30)
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/* PUBL_DXDLLCR */
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#define DXDLLCR_DLLDIS (1 << 31)
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#define DXDLLCR_DLLSRST (1 << 30)
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/* PUBL_DLLGCR */
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#define DLLGCR_SBIAS (1 << 30)
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/* PUBL_DXGCR */
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#define DQSRTT (1 << 9)
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#define DQRTT (1 << 10)
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/* PIR */
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#define PIR_INIT (1 << 0)
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#define PIR_DLLSRST (1 << 1)
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#define PIR_DLLLOCK (1 << 2)
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#define PIR_ZCAL (1 << 3)
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#define PIR_ITMSRST (1 << 4)
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#define PIR_DRAMRST (1 << 5)
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#define PIR_DRAMINIT (1 << 6)
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#define PIR_QSTRN (1 << 7)
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#define PIR_RVTRN (1 << 8)
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#define PIR_ICPC (1 << 16)
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#define PIR_DLLBYP (1 << 17)
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#define PIR_CTLDINIT (1 << 18)
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#define PIR_CLRSR (1 << 28)
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#define PIR_LOCKBYP (1 << 29)
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#define PIR_ZCALBYP (1 << 30)
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#define PIR_INITBYP (1u << 31)
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/* PGCR */
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#define PGCR_DFTLMT_SHIFT 3
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#define PGCR_DFTCMP_SHIFT 2
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#define PGCR_DQSCFG_SHIFT 1
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#define PGCR_ITMDMD_SHIFT 0
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/* PGSR */
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#define PGSR_IDONE (1 << 0)
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#define PGSR_DLDONE (1 << 1)
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#define PGSR_ZCDONE (1 << 2)
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#define PGSR_DIDONE (1 << 3)
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#define PGSR_DTDONE (1 << 4)
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#define PGSR_DTERR (1 << 5)
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#define PGSR_DTIERR (1 << 6)
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#define PGSR_DFTERR (1 << 7)
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#define PGSR_RVERR (1 << 8)
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#define PGSR_RVEIRR (1 << 9)
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/* PTR0 */
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#define PRT_ITMSRST_SHIFT 18
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#define PRT_DLLLOCK_SHIFT 6
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#define PRT_DLLSRST_SHIFT 0
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/* PTR1 */
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#define PRT_DINIT0_SHIFT 0
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#define PRT_DINIT1_SHIFT 19
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/* PTR2 */
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#define PRT_DINIT2_SHIFT 0
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#define PRT_DINIT3_SHIFT 17
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/* DCR */
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#define DDRMD_LPDDR 0
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#define DDRMD_DDR 1
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#define DDRMD_DDR2 2
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#define DDRMD_DDR3 3
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#define DDRMD_LPDDR2_LPDDR3 4
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#define DDRMD_MASK 7
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#define DDRMD_SHIFT 0
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#define PDQ_MASK 7
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#define PDQ_SHIFT 4
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/* DXCCR */
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#define DQSNRES_MASK 0xf
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#define DQSNRES_SHIFT 8
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#define DQSRES_MASK 0xf
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#define DQSRES_SHIFT 4
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/* DTPR */
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#define TDQSCKMAX_SHIFT 27
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#define TDQSCKMAX_MASK 7
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#define TDQSCK_SHIFT 24
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#define TDQSCK_MASK 7
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/* DSGCR */
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#define DQSGX_SHIFT 5
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#define DQSGX_MASK 7
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#define DQSGE_SHIFT 8
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#define DQSGE_MASK 7
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/* SCTL */
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#define INIT_STATE 0
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#define CFG_STATE 1
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#define GO_STATE 2
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#define SLEEP_STATE 3
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#define WAKEUP_STATE 4
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/* STAT */
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#define LP_TRIG_SHIFT 4
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#define LP_TRIG_MASK 7
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#define PCTL_STAT_MSK 7
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#define INIT_MEM 0
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#define CONFIG 1
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#define CONFIG_REQ 2
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#define ACCESS 3
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#define ACCESS_REQ 4
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#define LOW_POWER 5
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#define LOW_POWER_ENTRY_REQ 6
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#define LOW_POWER_EXIT_REQ 7
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/* ZQCR*/
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#define PD_OUTPUT_SHIFT 0
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#define PU_OUTPUT_SHIFT 5
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#define PD_ONDIE_SHIFT 10
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#define PU_ONDIE_SHIFT 15
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#define ZDEN_SHIFT 28
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/* DDLGCR */
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#define SBIAS_BYPASS (1 << 23)
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/* MCFG */
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#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24
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#define PD_IDLE_SHIFT 8
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#define MDDR_EN (2 << 22)
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#define LPDDR2_EN (3 << 22)
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#define DDR2_EN (0 << 5)
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#define DDR3_EN (1 << 5)
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#define LPDDR2_S2 (0 << 6)
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#define LPDDR2_S4 (1 << 6)
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#define MDDR_LPDDR2_BL_2 (0 << 20)
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#define MDDR_LPDDR2_BL_4 (1 << 20)
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#define MDDR_LPDDR2_BL_8 (2 << 20)
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#define MDDR_LPDDR2_BL_16 (3 << 20)
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#define DDR2_DDR3_BL_4 0
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#define DDR2_DDR3_BL_8 1
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#define TFAW_SHIFT 18
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#define PD_EXIT_SLOW (0 << 17)
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#define PD_EXIT_FAST (1 << 17)
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#define PD_TYPE_SHIFT 16
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#define BURSTLENGTH_SHIFT 20
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/* POWCTL */
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#define POWER_UP_START (1 << 0)
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/* POWSTAT */
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#define POWER_UP_DONE (1 << 0)
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/* MCMD */
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enum {
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DESELECT_CMD = 0,
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PREA_CMD,
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REF_CMD,
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MRS_CMD,
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ZQCS_CMD,
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ZQCL_CMD,
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RSTL_CMD,
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MRR_CMD = 8,
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DPDE_CMD,
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};
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#define LPDDR2_MA_SHIFT 4
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#define LPDDR2_MA_MASK 0xff
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#define LPDDR2_OP_SHIFT 12
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#define LPDDR2_OP_MASK 0xff
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#define START_CMD (1u << 31)
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/*
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* DDRCONF
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* [5:4] row(13+n)
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* [1:0] col(9+n), assume bw=2
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*/
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#define DDRCONF_ROW_SHIFT 4
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#define DDRCONF_COL_SHIFT 0
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/* DEVTODEV */
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#define BUSWRTORD_SHIFT 4
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#define BUSRDTOWR_SHIFT 2
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#define BUSRDTORD_SHIFT 0
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/* mr1 for ddr3 */
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#define DDR3_DLL_DISABLE 1
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#endif
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