147 lines
3.0 KiB
C
147 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <linux/sizes.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Not all memory is mapped in the MMU. So we need to restrict the
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* memory size so that U-Boot does not try to access it. Also, the
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* internal registers are located at 0xf000.0000 - 0xffff.ffff.
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* Currently only 2GiB are mapped for system memory. This is what
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* we pass to the U-Boot subsystem here.
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*/
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#define USABLE_RAM_SIZE 0x80000000
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ulong board_get_usable_ram_top(ulong total_size)
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{
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if (gd->ram_size > USABLE_RAM_SIZE)
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return USABLE_RAM_SIZE;
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return gd->ram_size;
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}
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/*
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* On ARMv8, MBus is not configured in U-Boot. To enable compilation
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* of the already implemented drivers, lets add a dummy version of
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* this function so that linking does not fail.
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*/
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const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
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{
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return NULL;
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}
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/* DRAM init code ... */
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#define MV_SIP_DRAM_SIZE 0x82000010
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static u64 a8k_dram_scan_ap_sz(void)
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{
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struct pt_regs pregs;
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pregs.regs[0] = MV_SIP_DRAM_SIZE;
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pregs.regs[1] = SOC_REGS_PHY_BASE;
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smc_call(&pregs);
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return pregs.regs[0];
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}
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static void a8k_dram_init_banksize(void)
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{
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/*
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* The firmware (ATF) leaves a 1G whole above the 3G mark for IO
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* devices. Higher RAM is mapped at 4G.
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*
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* Config 2 DRAM banks:
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* Bank 0 - max size 4G - 1G
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* Bank 1 - ram size - 4G + 1G
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*/
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phys_size_t max_bank0_size = SZ_4G - SZ_1G;
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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if (gd->ram_size <= max_bank0_size) {
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gd->bd->bi_dram[0].size = gd->ram_size;
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return;
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}
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gd->bd->bi_dram[0].size = max_bank0_size;
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if (CONFIG_NR_DRAM_BANKS > 1) {
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gd->bd->bi_dram[1].start = SZ_4G;
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gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
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}
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}
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__weak int dram_init_banksize(void)
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{
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if (CONFIG_IS_ENABLED(ARMADA_8K))
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a8k_dram_init_banksize();
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else
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fdtdec_setup_memory_banksize();
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return 0;
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}
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__weak int dram_init(void)
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{
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if (CONFIG_IS_ENABLED(ARMADA_8K)) {
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gd->ram_size = a8k_dram_scan_ap_sz();
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if (gd->ram_size != 0)
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return 0;
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}
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int arch_cpu_init(void)
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{
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/* Nothing to do (yet) */
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return 0;
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}
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int arch_early_init_r(void)
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{
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struct udevice *dev;
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int ret;
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int i;
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/*
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* Loop over all MISC uclass drivers to call the comphy code
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* and init all CP110 devices enabled in the DT
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*/
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i = 0;
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while (1) {
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/* Call the comphy code via the MISC uclass driver */
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ret = uclass_get_device(UCLASS_MISC, i++, &dev);
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/* We're done, once no further CP110 device is found */
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if (ret)
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break;
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}
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/* Cause the SATA device to do its early init */
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uclass_first_device(UCLASS_AHCI, &dev);
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#ifdef CONFIG_DM_PCI
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/* Trigger PCIe devices detection */
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pci_init();
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#endif
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return 0;
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}
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