118 lines
3.6 KiB
C
118 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _MV_DDR_SYS_ENV_LIB_H
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#define _MV_DDR_SYS_ENV_LIB_H
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#include "ddr_ml_wrapper.h"
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/* device revision */
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#define DEV_ID_REG 0x18238
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#define DEV_VERSION_ID_REG 0x1823c
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#define REVISON_ID_OFFS 8
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#define REVISON_ID_MASK 0xf00
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#define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
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#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
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#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
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#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
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#define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40))
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#define MPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 8)
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#define MPP_MASK(GPIO_NUM) (0xf << 4 * (GPIO_NUM - \
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(MPP_REG_NUM(GPIO_NUM) * 8)));
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#define GPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 32)
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#define GPP_MASK(GPIO_NUM) (1 << GPIO_NUM % 32)
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/* device ID */
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/* Board ID numbers */
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#define MARVELL_BOARD_ID_MASK 0x10
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/* Customer boards for A38x */
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#define A38X_CUSTOMER_BOARD_ID_BASE 0x0
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#define A38X_CUSTOMER_BOARD_ID0 (A38X_CUSTOMER_BOARD_ID_BASE + 0)
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#define A38X_CUSTOMER_BOARD_ID1 (A38X_CUSTOMER_BOARD_ID_BASE + 1)
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#define A38X_MV_MAX_CUSTOMER_BOARD_ID (A38X_CUSTOMER_BOARD_ID_BASE + 2)
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#define A38X_MV_CUSTOMER_BOARD_NUM (A38X_MV_MAX_CUSTOMER_BOARD_ID - \
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A38X_CUSTOMER_BOARD_ID_BASE)
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/* Marvell boards for A38x */
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#define A38X_MARVELL_BOARD_ID_BASE 0x10
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#define RD_NAS_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 0)
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#define DB_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 1)
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#define RD_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 2)
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#define DB_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 3)
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#define DB_GP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 4)
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#define DB_BP_6821_ID (A38X_MARVELL_BOARD_ID_BASE + 5)
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#define DB_AMC_6820_ID (A38X_MARVELL_BOARD_ID_BASE + 6)
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#define A38X_MV_MAX_MARVELL_BOARD_ID (A38X_MARVELL_BOARD_ID_BASE + 7)
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#define A38X_MV_MARVELL_BOARD_NUM (A38X_MV_MAX_MARVELL_BOARD_ID - \
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A38X_MARVELL_BOARD_ID_BASE)
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/* Marvell boards for A39x */
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#define A39X_MARVELL_BOARD_ID_BASE 0x30
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#define A39X_DB_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 0)
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#define A39X_RD_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 1)
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#define A39X_MV_MAX_MARVELL_BOARD_ID (A39X_MARVELL_BOARD_ID_BASE + 2)
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#define A39X_MV_MARVELL_BOARD_NUM (A39X_MV_MAX_MARVELL_BOARD_ID - \
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A39X_MARVELL_BOARD_ID_BASE)
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struct board_wakeup_gpio {
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u32 board_id;
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int gpio_num;
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};
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enum suspend_wakeup_status {
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SUSPEND_WAKEUP_DISABLED,
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SUSPEND_WAKEUP_ENABLED,
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SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED,
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};
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/*
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* GPIO status indication for Suspend Wakeup:
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* If suspend to RAM is supported and GPIO inidcation is implemented,
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* set the gpio number
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* If suspend to RAM is supported but GPIO indication is not implemented
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* set '-2'
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* If suspend to RAM is not supported set '-1'
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*/
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#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
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#ifdef CONFIG_ARMADA_38X
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#define MV_BOARD_WAKEUP_GPIO_INFO { \
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{A38X_CUSTOMER_BOARD_ID0, -1 }, \
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{A38X_CUSTOMER_BOARD_ID0, -1 }, \
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};
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#else
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#define MV_BOARD_WAKEUP_GPIO_INFO { \
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{A39X_CUSTOMER_BOARD_ID0, -1 }, \
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{A39X_CUSTOMER_BOARD_ID0, -1 }, \
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};
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#endif /* CONFIG_ARMADA_38X */
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#else
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#ifdef CONFIG_ARMADA_38X
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#define MV_BOARD_WAKEUP_GPIO_INFO { \
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{RD_NAS_68XX_ID, -2 }, \
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{DB_68XX_ID, -1 }, \
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{RD_AP_68XX_ID, -2 }, \
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{DB_AP_68XX_ID, -2 }, \
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{DB_GP_68XX_ID, -2 }, \
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{DB_BP_6821_ID, -2 }, \
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{DB_AMC_6820_ID, -2 }, \
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};
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#else
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#define MV_BOARD_WAKEUP_GPIO_INFO { \
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{A39X_RD_69XX_ID, -1 }, \
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{A39X_DB_69XX_ID, -1 }, \
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};
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#endif /* CONFIG_ARMADA_38X */
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#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
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enum suspend_wakeup_status mv_ddr_sys_env_suspend_wakeup_check(void);
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u32 mv_ddr_sys_env_get_cs_ena_from_reg(void);
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#endif /* _MV_DDR_SYS_ENV_LIB_H */
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