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Peng Fan 4a41a1a6f0 ddr: imx8m: Add DRAM PLL to generate 1000Mhz output 
We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
 		2020-01-08 13:20:08 +01:00
..
Kconfig driver: ddr: Refine the ddr init driver on imx8m 2019-10-08 16:36:37 +02:00
Makefile driver: ddr: Refine the ddr init driver on imx8m 2019-10-08 16:36:37 +02:00
ddr_init.c ddr: imx8m: Return error values from LPDDR4 training 2020-01-07 10:26:57 +01:00
ddrphy_csr.c
…
ddrphy_train.c ddr: imx8m: Return error values from LPDDR4 training 2020-01-07 10:26:57 +01:00
ddrphy_utils.c ddr: imx8m: Add DRAM PLL to generate 1000Mhz output 2020-01-08 13:20:08 +01:00
helper.c driver: ddr: Refine the ddr init driver on imx8m 2019-10-08 16:36:37 +02:00