170 lines
4.2 KiB
C
170 lines
4.2 KiB
C
/*
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* Copyright 2012-2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __PAMU_H
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#define __PAMU_H
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#define CONFIG_NUM_PAMU 16
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#define NUM_PPAACT_ENTRIES 512
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#define NUM_SPAACT_ENTRIES 256
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/* PAMU_OFFSET to the next pamu space in ccsr */
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#define PAMU_OFFSET 0x1000
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#define PAMU_TABLE_ALIGNMENT 0x00001000
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#define PAMU_PAGE_SHIFT 12
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#define PAMU_PAGE_SIZE 4096U
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#define PAACE_M_COHERENCE_REQ 0x01
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#define PAACE_DA_HOST_CR 0x80
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#define PAACE_DA_HOST_CR_SHIFT 7
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#define PAACE_AF_PT 0x00000002
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#define PAACE_AF_PT_SHIFT 1
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#define PAACE_PT_PRIMARY 0x0
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#define PAACE_PT_SECONDARY 0x1
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#define PPAACE_AF_WBAL 0xfffff000
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#define PPAACE_AF_WBAL_SHIFT 12
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#define OME_NUMBER_ENTRIES 16 /* based on P4080 2.0 silicon plan */
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#define PAACE_IA_CID 0x00FF0000
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#define PAACE_IA_CID_SHIFT 16
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#define PAACE_IA_WCE 0x000000F0
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#define PAACE_IA_WCE_SHIFT 4
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#define PAACE_IA_ATM 0x0000000C
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#define PAACE_IA_ATM_SHIFT 2
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#define PAACE_IA_OTM 0x00000003
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#define PAACE_IA_OTM_SHIFT 0
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#define PAACE_OTM_NO_XLATE 0x00
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#define PAACE_OTM_IMMEDIATE 0x01
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#define PAACE_OTM_INDEXED 0x02
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#define PAACE_OTM_RESERVED 0x03
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#define PAACE_ATM_NO_XLATE 0x00
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#define PAACE_ATM_WINDOW_XLATE 0x01
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#define PAACE_ATM_PAGE_XLATE 0x02
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#define PAACE_ATM_WIN_PG_XLATE \
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(PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
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#define PAACE_WIN_TWBAL 0xfffff000
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#define PAACE_WIN_TWBAL_SHIFT 12
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#define PAACE_WIN_SWSE 0x00000fc0
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#define PAACE_WIN_SWSE_SHIFT 6
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#define PAACE_AF_AP 0x00000018
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#define PAACE_AF_AP_SHIFT 3
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#define PAACE_AF_DD 0x00000004
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#define PAACE_AF_DD_SHIFT 2
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#define PAACE_AF_PT 0x00000002
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#define PAACE_AF_PT_SHIFT 1
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#define PAACE_AF_V 0x00000001
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#define PAACE_AF_V_SHIFT 0
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#define PPAACE_AF_WSE 0x00000fc0
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#define PPAACE_AF_WSE_SHIFT 6
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#define PPAACE_AF_MW 0x00000020
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#define PPAACE_AF_MW_SHIFT 5
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#define PAACE_AP_PERMS_DENIED 0x0
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#define PAACE_AP_PERMS_QUERY 0x1
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#define PAACE_AP_PERMS_UPDATE 0x2
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#define PAACE_AP_PERMS_ALL 0x3
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#define SPAACE_AF_LIODN 0xffff0000
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#define SPAACE_AF_LIODN_SHIFT 16
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#define PAACE_V_VALID 0x1
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#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << \
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(m##_SHIFT)) & (m)))
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#define get_bf(v, m) (((v) & (m)) >> (m##_SHIFT))
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#define DEFAULT_NUM_SUBWINDOWS 128
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#define PAMU_PCR_OFFSET 0xc10
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#define PAMU_PCR_PE 0x40000000
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struct pamu_addr_tbl {
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phys_addr_t start_addr[10];
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phys_addr_t end_addr[10];
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phys_size_t size[10];
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};
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struct paace {
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/* PAACE Offset 0x00 */
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uint32_t wbah; /* only valid for Primary PAACE */
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uint32_t addr_bitfields; /* See P/S PAACE_AF_* */
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/* PAACE Offset 0x08 */
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/* Interpretation of first 32 bits dependent on DD above */
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union {
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struct {
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/* Destination ID, see PAACE_DID_* defines */
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uint8_t did;
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/* Partition ID */
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uint8_t pid;
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/* Snoop ID */
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uint8_t snpid;
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/* coherency_required : 1 reserved : 7 */
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uint8_t coherency_required; /* See PAACE_DA_* */
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} to_host;
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struct {
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/* Destination ID, see PAACE_DID_* defines */
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uint8_t did;
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uint8_t reserved1;
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uint16_t reserved2;
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} to_io;
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} domain_attr;
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/* Implementation attributes + window count + address & operation
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* translation modes
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*/
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uint32_t impl_attr; /* See PAACE_IA_* */
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/* PAACE Offset 0x10 */
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/* Translated window base address */
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uint32_t twbah;
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uint32_t win_bitfields; /* See PAACE_WIN_* */
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/* PAACE Offset 0x18 */
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/* first secondary paace entry */
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uint32_t fspi; /* only valid for Primary PAACE */
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union {
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struct {
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uint8_t ioea;
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uint8_t moea;
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uint8_t ioeb;
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uint8_t moeb;
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} immed_ot;
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struct {
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uint16_t reserved;
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uint16_t omi;
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} index_ot;
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} op_encode;
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/* PAACE Offset 0x20 */
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uint32_t reserved1[2]; /* not currently implemented */
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/* PAACE Offset 0x28 */
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uint32_t reserved2[2]; /* not currently implemented */
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/* PAACE Offset 0x30 */
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uint32_t reserved3[2]; /* not currently implemented */
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/* PAACE Offset 0x38 */
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uint32_t reserved4[2]; /* not currently implemented */
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};
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int pamu_init(void);
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void pamu_enable(void);
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void pamu_disable(void);
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int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn);
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int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s);
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#endif
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