130 lines
3.1 KiB
C
130 lines
3.1 KiB
C
/*
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* Freescale iMX51 ATA driver
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on code by:
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* Mahesh Mahadevan <mahesh.mahadevan@freescale.com>
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*
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* Based on code from original FSL ATA driver, which is
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* part of eCos, the Embedded Configurable Operating System.
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* Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <config.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <ide.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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/* MXC ATA register offsets */
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struct mxc_ata_config_regs {
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u8 time_off; /* 0x00 */
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u8 time_on;
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u8 time_1;
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u8 time_2w;
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u8 time_2r;
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u8 time_ax;
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u8 time_pio_rdx;
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u8 time_4;
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u8 time_9;
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u8 time_m;
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u8 time_jn;
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u8 time_d;
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u8 time_k;
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u8 time_ack;
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u8 time_env;
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u8 time_udma_rdx;
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u8 time_zah; /* 0x10 */
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u8 time_mlix;
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u8 time_dvh;
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u8 time_dzfs;
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u8 time_dvs;
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u8 time_cvh;
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u8 time_ss;
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u8 time_cyc;
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u32 fifo_data_32; /* 0x18 */
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u32 fifo_data_16;
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u32 fifo_fill;
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u32 ata_control;
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u32 interrupt_pending;
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u32 interrupt_enable;
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u32 interrupt_clear;
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u32 fifo_alarm;
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};
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struct mxc_data_hdd_regs {
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u32 drive_data; /* 0xa0 */
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u32 drive_features;
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u32 drive_sector_count;
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u32 drive_sector_num;
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u32 drive_cyl_low;
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u32 drive_cyl_high;
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u32 drive_dev_head;
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u32 command;
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u32 status;
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u32 alt_status;
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};
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/* PIO timing table */
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#define NR_PIO_SPECS 5
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static uint16_t pio_t1[NR_PIO_SPECS] = { 70, 50, 30, 30, 25 };
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static uint16_t pio_t2_8[NR_PIO_SPECS] = { 290, 290, 290, 80, 70 };
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static uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 };
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static uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 };
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static uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 };
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#define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8)
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static void set_ata_bus_timing(unsigned char mode)
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{
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uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK);
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struct mxc_ata_config_regs *ata_regs;
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ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
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if (mode >= NR_PIO_SPECS)
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return;
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/* Write TIME_OFF/ON/1/2W */
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writeb(3, &ata_regs->time_off);
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writeb(3, &ata_regs->time_on);
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writeb((pio_t1[mode] + T) / T, &ata_regs->time_1);
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writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2w);
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/* Write TIME_2R/AX/RDX/4 */
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writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2r);
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writeb((pio_tA[mode] + T) / T + 2, &ata_regs->time_ax);
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writeb(1, &ata_regs->time_pio_rdx);
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writeb((pio_t4[mode] + T) / T, &ata_regs->time_4);
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/* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */
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writeb((pio_t9[mode] + T) / T, &ata_regs->time_9);
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}
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int ide_preinit(void)
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{
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struct mxc_ata_config_regs *ata_regs;
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ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
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/* 46.3.3.4 @ FSL iMX51 manual */
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/* FIFO normal op., drive reset */
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writel(0x80, &ata_regs->ata_control);
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/* FIFO normal op., drive not reset */
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writel(0xc0, &ata_regs->ata_control);
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/* Configure the PIO timing */
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set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE);
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/* 46.3.3.4 @ FSL iMX51 manual */
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/* Drive not reset, IORDY handshake */
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writel(0x41, &ata_regs->ata_control);
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return 0;
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}
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