465 lines
15 KiB
C
465 lines
15 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_HWS_HW_TRAINING_DEF_H
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#define _DDR3_HWS_HW_TRAINING_DEF_H
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#define SAR_DDR3_FREQ_MASK 0xfe00000
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#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | \
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((fab & 0xf) << 24))
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#define MAX_CS 4
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#define MIN_DIMM_ADDR 0x50
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#define FAR_END_DIMM_ADDR 0x50
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#define MAX_DIMM_ADDR 0x60
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#define SDRAM_CS_SIZE 0xfffffff
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#define SDRAM_CS_BASE 0x0
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#define SDRAM_DIMM_SIZE 0x80000000
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#define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100))
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#define CPU_MRVL_ID_OFFSET 0x10
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#define SAR1_CPU_CORE_MASK 0x38000000
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#define SAR1_CPU_CORE_OFFSET 27
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#define NEW_FABRIC_TWSI_ADDR 0x4e
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#ifdef DB_784MP_GP
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#define BUS_WIDTH_ECC_TWSI_ADDR 0x4e
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#else
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#define BUS_WIDTH_ECC_TWSI_ADDR 0x4f
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#endif
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#define MV_MAX_DDR3_STATIC_SIZE 50
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#define MV_DDR3_MODES_NUMBER 30
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#define RESUME_RL_PATTERNS_ADDR 0xfe0000
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#define RESUME_RL_PATTERNS_SIZE 0x100
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#define RESUME_TRAINING_VALUES_ADDR (RESUME_RL_PATTERNS_ADDR + \
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RESUME_RL_PATTERNS_SIZE)
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#define RESUME_TRAINING_VALUES_MAX 0xcd0
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#define BOOT_INFO_ADDR (RESUME_RL_PATTERNS_ADDR + 0x1000)
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#define CHECKSUM_RESULT_ADDR (BOOT_INFO_ADDR + 0x1000)
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#define NUM_OF_REGISTER_ADDR (CHECKSUM_RESULT_ADDR + 4)
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#define SUSPEND_MAGIC_WORD 0xdeadb002
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#define REGISTER_LIST_END 0xffffffff
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/* MISC */
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#define INTER_REGS_BASE SOC_REGS_PHY_BASE
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/* DDR */
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#define REG_SDRAM_CONFIG_ADDR 0x1400
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#define REG_SDRAM_CONFIG_MASK 0x9fffffff
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#define REG_SDRAM_CONFIG_RFRS_MASK 0x3fff
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#define REG_SDRAM_CONFIG_WIDTH_OFFS 15
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#define REG_SDRAM_CONFIG_REGDIMM_OFFS 17
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#define REG_SDRAM_CONFIG_ECC_OFFS 18
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#define REG_SDRAM_CONFIG_IERR_OFFS 19
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#define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS 28
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#define REG_SDRAM_CONFIG_RSTRD_OFFS 30
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#define REG_SDRAM_PINS_MUX 0x19d4
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#define REG_DUNIT_CTRL_LOW_ADDR 0x1404
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#define REG_DUNIT_CTRL_LOW_2T_OFFS 3
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#define REG_DUNIT_CTRL_LOW_2T_MASK 0x3
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#define REG_DUNIT_CTRL_LOW_DPDE_OFFS 14
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#define REG_SDRAM_TIMING_LOW_ADDR 0x1408
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#define REG_SDRAM_TIMING_HIGH_ADDR 0x140c
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#define REG_SDRAM_TIMING_H_R2R_OFFS 7
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#define REG_SDRAM_TIMING_H_R2R_MASK 0x3
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#define REG_SDRAM_TIMING_H_R2W_W2R_OFFS 9
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#define REG_SDRAM_TIMING_H_R2W_W2R_MASK 0x3
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#define REG_SDRAM_TIMING_H_W2W_OFFS 11
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#define REG_SDRAM_TIMING_H_W2W_MASK 0x1f
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#define REG_SDRAM_TIMING_H_R2R_H_OFFS 19
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#define REG_SDRAM_TIMING_H_R2R_H_MASK 0x7
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#define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS 22
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#define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK 0x7
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#define REG_SDRAM_ADDRESS_CTRL_ADDR 0x1410
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#define REG_SDRAM_ADDRESS_SIZE_OFFS 2
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#define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS 18
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#define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS 4
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#define REG_SDRAM_OPEN_PAGES_ADDR 0x1414
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#define REG_SDRAM_OPERATION_CS_OFFS 8
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#define REG_SDRAM_OPERATION_ADDR 0x1418
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#define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS 24
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#define REG_SDRAM_OPERATION_CWA_DATA_OFFS 20
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#define REG_SDRAM_OPERATION_CWA_DATA_MASK 0xf
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#define REG_SDRAM_OPERATION_CWA_RC_OFFS 16
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#define REG_SDRAM_OPERATION_CWA_RC_MASK 0xf
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#define REG_SDRAM_OPERATION_CMD_MR0 0xf03
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#define REG_SDRAM_OPERATION_CMD_MR1 0xf04
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#define REG_SDRAM_OPERATION_CMD_MR2 0xf08
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#define REG_SDRAM_OPERATION_CMD_MR3 0xf09
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#define REG_SDRAM_OPERATION_CMD_RFRS 0xf02
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#define REG_SDRAM_OPERATION_CMD_CWA 0xf0e
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#define REG_SDRAM_OPERATION_CMD_RFRS_DONE 0xf
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#define REG_SDRAM_OPERATION_CMD_MASK 0xf
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#define REG_SDRAM_OPERATION_CS_OFFS 8
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#define REG_OUDDR3_TIMING_ADDR 0x142c
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#define REG_SDRAM_MODE_ADDR 0x141c
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#define REG_SDRAM_EXT_MODE_ADDR 0x1420
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#define REG_DDR_CONT_HIGH_ADDR 0x1424
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#define REG_ODT_TIME_LOW_ADDR 0x1428
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#define REG_ODT_ON_CTL_RD_OFFS 12
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#define REG_ODT_OFF_CTL_RD_OFFS 16
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#define REG_SDRAM_ERROR_ADDR 0x1454
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#define REG_SDRAM_AUTO_PWR_SAVE_ADDR 0x1474
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#define REG_ODT_TIME_HIGH_ADDR 0x147c
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#define REG_SDRAM_INIT_CTRL_ADDR 0x1480
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#define REG_SDRAM_INIT_CTRL_OFFS 0
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#define REG_SDRAM_INIT_CKE_ASSERT_OFFS 2
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#define REG_SDRAM_INIT_RESET_DEASSERT_OFFS 3
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#define REG_SDRAM_INIT_RESET_MASK_OFFS 1
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#define REG_SDRAM_ODT_CTRL_LOW_ADDR 0x1494
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#define REG_SDRAM_ODT_CTRL_HIGH_ADDR 0x1498
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#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0x0
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#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA 0x3
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#define REG_DUNIT_ODT_CTRL_ADDR 0x149c
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#define REG_DUNIT_ODT_CTRL_OVRD_OFFS 8
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#define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS 9
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#define REG_DRAM_FIFO_CTRL_ADDR 0x14a0
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#define REG_DRAM_AXI_CTRL_ADDR 0x14a8
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#define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS 0
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#define REG_METAL_MASK_ADDR 0x14b0
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#define REG_METAL_MASK_MASK 0xdfffffff
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#define REG_METAL_MASK_RETRY_OFFS 0
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#define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR 0x14c0
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#define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR 0x14c4
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#define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR 0x14c8
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#define REG_DRAM_MAIN_PADS_CAL_ADDR 0x14cc
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#define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR 0x17c8
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#define REG_CS_SIZE_SCRATCH_ADDR 0x1504
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#define REG_DYNAMIC_POWER_SAVE_ADDR 0x1520
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#define REG_DDR_IO_ADDR 0x1524
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#define REG_DDR_IO_CLK_RATIO_OFFS 15
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#define REG_DFS_ADDR 0x1528
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#define REG_DFS_DLLNEXTSTATE_OFFS 0
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#define REG_DFS_BLOCK_OFFS 1
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#define REG_DFS_SR_OFFS 2
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#define REG_DFS_ATSR_OFFS 3
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#define REG_DFS_RECONF_OFFS 4
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#define REG_DFS_CL_NEXT_STATE_OFFS 8
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#define REG_DFS_CL_NEXT_STATE_MASK 0xf
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#define REG_DFS_CWL_NEXT_STATE_OFFS 12
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#define REG_DFS_CWL_NEXT_STATE_MASK 0x7
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#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
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#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1f
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#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8
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#define REG_READ_DATA_READY_DELAYS_ADDR 0x153c
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#define REG_READ_DATA_READY_DELAYS_MASK 0x1f
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#define REG_READ_DATA_READY_DELAYS_OFFS 8
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#define START_BURST_IN_ADDR 1
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#define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488
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#define REG_DRAM_TRAINING_ADDR 0x15b0
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#define REG_DRAM_TRAINING_LOW_FREQ_OFFS 0
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#define REG_DRAM_TRAINING_PATTERNS_OFFS 4
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#define REG_DRAM_TRAINING_MED_FREQ_OFFS 2
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#define REG_DRAM_TRAINING_WL_OFFS 3
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#define REG_DRAM_TRAINING_RL_OFFS 6
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#define REG_DRAM_TRAINING_DQS_RX_OFFS 15
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#define REG_DRAM_TRAINING_DQS_TX_OFFS 16
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#define REG_DRAM_TRAINING_CS_OFFS 20
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#define REG_DRAM_TRAINING_RETEST_OFFS 24
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#define REG_DRAM_TRAINING_DFS_FREQ_OFFS 27
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#define REG_DRAM_TRAINING_DFS_REQ_OFFS 29
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#define REG_DRAM_TRAINING_ERROR_OFFS 30
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#define REG_DRAM_TRAINING_AUTO_OFFS 31
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#define REG_DRAM_TRAINING_RETEST_PAR 0x3
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#define REG_DRAM_TRAINING_RETEST_MASK 0xf8ffffff
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#define REG_DRAM_TRAINING_CS_MASK 0xff0fffff
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#define REG_DRAM_TRAINING_PATTERNS_MASK 0xff0f0000
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#define REG_DRAM_TRAINING_1_ADDR 0x15b4
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#define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS 16
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#define REG_DRAM_TRAINING_2_ADDR 0x15b8
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#define REG_DRAM_TRAINING_2_OVERRUN_OFFS 17
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#define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4
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#define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3
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#define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2
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#define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1
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#define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0
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#define REG_DRAM_TRAINING_PATTERN_BASE_ADDR 0x15bc
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#define REG_DRAM_TRAINING_PATTERN_BASE_OFFS 3
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#define REG_TRAINING_DEBUG_2_ADDR 0x15c4
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#define REG_TRAINING_DEBUG_2_OFFS 16
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#define REG_TRAINING_DEBUG_2_MASK 0x3
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#define REG_TRAINING_DEBUG_3_ADDR 0x15c8
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#define REG_TRAINING_DEBUG_3_OFFS 3
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#define REG_TRAINING_DEBUG_3_MASK 0x7
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#define MR_CS_ADDR_OFFS 4
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#define REG_DDR3_MR0_ADDR 0x15d0
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#define REG_DDR3_MR0_CS_ADDR 0x1870
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#define REG_DDR3_MR0_CL_MASK 0x74
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#define REG_DDR3_MR0_CL_OFFS 2
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#define REG_DDR3_MR0_CL_HIGH_OFFS 3
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#define CL_MASK 0xf
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#define REG_DDR3_MR1_ADDR 0x15d4
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#define REG_DDR3_MR1_CS_ADDR 0x1874
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#define REG_DDR3_MR1_RTT_MASK 0xfffffdbb
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#define REG_DDR3_MR1_DLL_ENA_OFFS 0
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#define REG_DDR3_MR1_RTT_DISABLED 0x0
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#define REG_DDR3_MR1_RTT_RZQ2 0x40
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#define REG_DDR3_MR1_RTT_RZQ4 0x2
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#define REG_DDR3_MR1_RTT_RZQ6 0x42
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#define REG_DDR3_MR1_RTT_RZQ8 0x202
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#define REG_DDR3_MR1_RTT_RZQ12 0x4
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/* WL-disabled, OB-enabled */
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#define REG_DDR3_MR1_OUTBUF_WL_MASK 0xffffef7f
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/* Output Buffer Disabled */
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#define REG_DDR3_MR1_OUTBUF_DIS_OFFS 12
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#define REG_DDR3_MR1_WL_ENA_OFFS 7
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#define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */
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#define REG_DDR3_MR1_ODT_MASK 0xfffffdbb
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#define REG_DDR3_MR2_ADDR 0x15d8
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#define REG_DDR3_MR2_CS_ADDR 0x1878
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#define REG_DDR3_MR2_CWL_OFFS 3
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#define REG_DDR3_MR2_CWL_MASK 0x7
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#define REG_DDR3_MR2_ODT_MASK 0xfffff9ff
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#define REG_DDR3_MR3_ADDR 0x15dc
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#define REG_DDR3_MR3_CS_ADDR 0x187c
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#define REG_DDR3_RANK_CTRL_ADDR 0x15e0
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#define REG_DDR3_RANK_CTRL_CS_ENA_MASK 0xf
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#define REG_DDR3_RANK_CTRL_MIRROR_OFFS 4
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#define REG_ZQC_CONF_ADDR 0x15e4
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#define REG_DRAM_PHY_CONFIG_ADDR 0x15ec
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#define REG_DRAM_PHY_CONFIG_MASK 0x3fffffff
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#define REG_ODPG_CNTRL_ADDR 0x1600
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#define REG_ODPG_CNTRL_OFFS 21
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#define REG_PHY_LOCK_MASK_ADDR 0x1670
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#define REG_PHY_LOCK_MASK_MASK 0xfffff000
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#define REG_PHY_LOCK_STATUS_ADDR 0x1674
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#define REG_PHY_LOCK_STATUS_LOCK_OFFS 9
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#define REG_PHY_LOCK_STATUS_LOCK_MASK 0xfff
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#define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK 0x7ff
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#define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16a0
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#define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xc0000000
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#define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD 0x80000000
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#define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE 0x80000000
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#define REG_PHY_BC_OFFS 27
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#define REG_PHY_CNTRL_OFFS 26
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#define REG_PHY_CS_OFFS 16
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#define REG_PHY_DQS_REF_DLY_OFFS 10
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#define REG_PHY_PHASE_OFFS 8
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#define REG_PHY_PUP_OFFS 22
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#define REG_TRAINING_WL_ADDR 0x16ac
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#define REG_TRAINING_WL_CS_MASK 0xfffffffc
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#define REG_TRAINING_WL_UPD_OFFS 2
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#define REG_TRAINING_WL_CS_DONE_OFFS 3
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#define REG_TRAINING_WL_RATIO_MASK 0xffffff0f
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#define REG_TRAINING_WL_1TO1 0x50
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#define REG_TRAINING_WL_2TO1 0x10
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#define REG_TRAINING_WL_DELAYEXP_MASK 0x20000000
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#define REG_TRAINING_WL_RESULTS_MASK 0x000001ff
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#define REG_TRAINING_WL_RESULTS_OFFS 20
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#define REG_REGISTERED_DRAM_CTRL_ADDR 0x16d0
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#define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS 15
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#define REG_REGISTERED_DRAM_CTRL_PARITY_MASK 0x3f
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/* DLB */
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#define REG_STATIC_DRAM_DLB_CONTROL 0x1700
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#define DLB_BUS_OPTIMIZATION_WEIGHTS_REG 0x1704
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#define DLB_AGING_REGISTER 0x1708
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#define DLB_EVICTION_CONTROL_REG 0x170c
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#define DLB_EVICTION_TIMERS_REGISTER_REG 0x1710
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#define DLB_USER_COMMAND_REG 0x1714
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#define DLB_BUS_WEIGHTS_DIFF_CS 0x1770
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#define DLB_BUS_WEIGHTS_DIFF_BG 0x1774
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#define DLB_BUS_WEIGHTS_SAME_BG 0x1778
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#define DLB_BUS_WEIGHTS_RD_WR 0x177c
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#define DLB_BUS_WEIGHTS_ATTR_SYS_PRIO 0x1780
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#define DLB_MAIN_QUEUE_MAP 0x1784
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#define DLB_LINE_SPLIT 0x1788
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#define DLB_ENABLE 0x1
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#define DLB_WRITE_COALESING (0x1 << 2)
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#define DLB_AXI_PREFETCH_EN (0x1 << 3)
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#define DLB_MBUS_PREFETCH_EN (0x1 << 4)
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#define PREFETCH_N_LN_SZ_TR (0x1 << 6)
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#define DLB_INTERJECTION_ENABLE (0x1 << 3)
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/* CPU */
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#define REG_BOOTROM_ROUTINE_ADDR 0x182d0
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#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12
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#define REG_DRAM_INIT_CTRL_STATUS_ADDR 0x18488
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#define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS 16
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#define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO 0x000200ff
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#define REG_DRAM_INIT_CTRL_STATUS_2_ADDR 0x1488
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#define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700
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#define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704
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#define REG_CPU_DIV_CLK_CTRL_2_ADDR 0x18708
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#define REG_CPU_DIV_CLK_CTRL_3_ADDR 0x1870c
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#define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK 0xffffc0ff
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#define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS 8
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#define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710
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#define REG_CPU_DIV_CLK_STATUS_0_ADDR 0x18718
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#define REG_CPU_DIV_CLK_ALL_STABLE_OFFS 8
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#define REG_CPU_PLL_CTRL_0_ADDR 0x1871c
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#define REG_CPU_PLL_STATUS_0_ADDR 0x18724
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#define REG_CORE_DIV_CLK_CTRL_ADDR 0x18740
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#define REG_CORE_DIV_CLK_STATUS_ADDR 0x18744
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#define REG_DDRPHY_APLL_CTRL_ADDR 0x18780
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#define REG_DDRPHY_APLL_CTRL_2_ADDR 0x18784
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#define REG_SFABRIC_CLK_CTRL_ADDR 0x20858
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#define REG_SFABRIC_CLK_CTRL_SMPL_OFFS 8
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/* DRAM Windows */
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#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
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#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
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#define REG_XBAR_WIN_4_BASE_ADDR 0x20044
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#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
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#define REG_FASTPATH_WIN_0_CTRL_ADDR 0x20184
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#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
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/* SRAM */
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#define REG_CDI_CONFIG_ADDR 0x20220
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#define REG_SRAM_WINDOW_0_ADDR 0x20240
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#define REG_SRAM_WINDOW_0_ENA_OFFS 0
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#define REG_SRAM_WINDOW_1_ADDR 0x20244
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#define REG_SRAM_L2_ENA_ADDR 0x8500
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#define REG_SRAM_CLEAN_BY_WAY_ADDR 0x87bc
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/* Timers */
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#define REG_TIMERS_CTRL_ADDR 0x20300
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#define REG_TIMERS_EVENTS_ADDR 0x20304
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#define REG_TIMER0_VALUE_ADDR 0x20314
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#define REG_TIMER1_VALUE_ADDR 0x2031c
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#define REG_TIMER0_ENABLE_MASK 0x1
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#define MV_BOARD_REFCLK_25MHZ 25000000
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#define CNTMR_RELOAD_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x10 + (tmr * 8))
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#define CNTMR_VAL_REG(tmr) (REG_TIMERS_CTRL_ADDR + 0x14 + (tmr * 8))
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#define CNTMR_CTRL_REG(tmr) (REG_TIMERS_CTRL_ADDR)
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#define CTCR_ARM_TIMER_EN_OFFS(timer) (timer * 2)
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#define CTCR_ARM_TIMER_EN_MASK(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
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#define CTCR_ARM_TIMER_EN(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
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#define CTCR_ARM_TIMER_AUTO_OFFS(timer) (1 + (timer * 2))
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#define CTCR_ARM_TIMER_AUTO_MASK(timer) (1 << CTCR_ARM_TIMER_EN_OFFS(timer))
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#define CTCR_ARM_TIMER_AUTO_EN(timer) (1 << CTCR_ARM_TIMER_AUTO_OFFS(timer))
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/* PMU */
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#define REG_PMU_I_F_CTRL_ADDR 0x1c090
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#define REG_PMU_DUNIT_BLK_OFFS 16
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#define REG_PMU_DUNIT_RFRS_OFFS 20
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#define REG_PMU_DUNIT_ACK_OFFS 24
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/* MBUS */
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#define MBUS_UNITS_PRIORITY_CONTROL_REG (MBUS_REGS_OFFSET + 0x420)
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#define FABRIC_UNITS_PRIORITY_CONTROL_REG (MBUS_REGS_OFFSET + 0x424)
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#define MBUS_UNITS_PREFETCH_CONTROL_REG (MBUS_REGS_OFFSET + 0x428)
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#define FABRIC_UNITS_PREFETCH_CONTROL_REG (MBUS_REGS_OFFSET + 0x42c)
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#define REG_PM_STAT_MASK_ADDR 0x2210c
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#define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS 16
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#define REG_PM_EVENT_STAT_MASK_ADDR 0x22120
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#define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS 17
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#define REG_PM_CTRL_CONFIG_ADDR 0x22104
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#define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS 18
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#define REG_FABRIC_LOCAL_IRQ_MASK_ADDR 0x218c4
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#define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS 18
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/* Controller revision info */
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#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
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#define PCCRIR_REVID_OFFS 0 /* Revision ID */
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#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
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/* Power Management Clock Gating Control Register */
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#define POWER_MNG_CTRL_REG 0x18220
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#define PEX_DEVICE_AND_VENDOR_ID 0x000
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#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg))
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#define PMC_PEXSTOPCLOCK_OFFS(p) ((p) < 8 ? (5 + (p)) : (18 + (p)))
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#define PMC_PEXSTOPCLOCK_MASK(p) (1 << PMC_PEXSTOPCLOCK_OFFS(p))
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#define PMC_PEXSTOPCLOCK_EN(p) (1 << PMC_PEXSTOPCLOCK_OFFS(p))
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#define PMC_PEXSTOPCLOCK_STOP(p) (0 << PMC_PEXSTOPCLOCK_OFFS(p))
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/* TWSI */
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#define TWSI_DATA_ADDR_MASK 0x7
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#define TWSI_DATA_ADDR_OFFS 1
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/* General */
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#define MAX_CS 4
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/* Frequencies */
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#define FAB_OPT 21
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#define CLK_CPU 12
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#define CLK_VCO (2 * CLK_CPU)
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#define CLK_DDR 12
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/* CPU Frequencies: */
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#define CLK_CPU_1000 0
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#define CLK_CPU_1066 1
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#define CLK_CPU_1200 2
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#define CLK_CPU_1333 3
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#define CLK_CPU_1500 4
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#define CLK_CPU_1666 5
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#define CLK_CPU_1800 6
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#define CLK_CPU_2000 7
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#define CLK_CPU_600 8
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#define CLK_CPU_667 9
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#define CLK_CPU_800 0xa
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/* Extra Cpu Frequencies: */
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#define CLK_CPU_1600 11
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#define CLK_CPU_2133 12
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#define CLK_CPU_2200 13
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#define CLK_CPU_2400 14
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#endif /* _DDR3_HWS_HW_TRAINING_DEF_H */
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