753 lines
17 KiB
Plaintext
753 lines
17 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Copyright 2019 Toradex AG
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "imx6q.dtsi"
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/ {
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model = "Toradex Apalis iMX6Q/D";
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compatible = "toradex,apalis_imx6q", "fsl,imx6q";
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/* Will be filled by the bootloader */
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memory@10000000 {
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device_type = "memory";
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reg = <0x10000000 0>;
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};
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aliases {
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mmc0 = &usdhc3;
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mmc1 = &usdhc1;
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mmc2 = &usdhc2;
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usb0 = &usbotg; /* required for ums */
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ethernet0 = &fec;
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};
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chosen {
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stdout-path = &uart1;
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};
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reg_module_3v3: regulator-module-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "+V3.3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_usb_otg_vbus: regulator-usb-otg-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* USBO1_EN */
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enable-active-high;
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};
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/* on-module USB hub */
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reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
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regulator-name = "usb_host_vbus_hub";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <2000>;
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enable-active-high;
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};
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reg_usb_host_vbus: regulator-usb-host-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
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regulator-name = "usb_host_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* USBH_EN */
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enable-active-high;
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vin-supply = <®_usb_host_vbus_hub>;
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};
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};
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/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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};
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/*
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* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
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* touch screen controller
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*/
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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pmic: pfuze100@8 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw3a_reg: sw3a {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-boot-on;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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regulator-boot-on;
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regulator-always-on;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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/*
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* I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
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* board)
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*/
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c3>;
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pinctrl-1 = <&pinctrl_i2c3_recovery>;
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scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii";
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phy-handle = <ðphy>;
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phy-reset-duration = <10>;
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phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@7 {
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interrupt-parent = <&gpio1>;
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interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
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reg = <7>;
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};
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};
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};
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/* Apalis Serial ATA */
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&sata {
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status = "okay";
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};
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/* Apalis UART1 */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
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fsl,dte-mode;
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uart-has-rtscts;
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status = "okay";
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};
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/* Apalis UART2 */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2_dte>;
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fsl,dte-mode;
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uart-has-rtscts;
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status = "okay";
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};
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/* Apalis UART3 */
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4_dte>;
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fsl,dte-mode;
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status = "okay";
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};
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/* Apalis UART4 */
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5_dte>;
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fsl,dte-mode;
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status = "okay";
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};
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/* Apalis USBH[2|3|4] */
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&usbh1 {
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dr_mode = "host";
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vbus-supply = <®_usb_host_vbus>;
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status = "okay";
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};
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/* Apalis USBO1 */
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&usbotg {
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dr_mode = "host";
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vbus-supply = <®_usb_otg_vbus>;
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status = "okay";
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};
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/* Apalis MMC1 */
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
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cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; /* MMC1_CD */
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disable-wp;
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no-1-8-v;
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status = "okay";
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};
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/* Apalis SD1 */
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
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cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* SD1_CD */
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disable-wp;
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no-1-8-v;
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status = "okay";
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};
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/* eMMC */
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&usdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3>;
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vqmmc-supply = <®_module_3v3>;
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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status = "okay";
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};
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&iomuxc {
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pinctrl_apalis_gpio1: gpio2io04grp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
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>;
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};
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pinctrl_apalis_gpio2: gpio2io05grp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
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>;
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};
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pinctrl_apalis_gpio3: gpio2io06grp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
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>;
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};
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pinctrl_apalis_gpio4: gpio2io07grp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
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>;
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};
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pinctrl_apalis_gpio5: gpio6io10grp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
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>;
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};
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pinctrl_apalis_gpio6: gpio6io09grp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
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>;
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};
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pinctrl_apalis_gpio7: gpio1io02grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
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>;
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};
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pinctrl_apalis_gpio8: gpio1io06grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
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>;
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};
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pinctrl_audmux: audmuxgrp {
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fsl,pins = <
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MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
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MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
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MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
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MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
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/* SGTL5000 sys_mclk */
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MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
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>;
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};
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pinctrl_cam_mclk: cammclkgrp {
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fsl,pins = <
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/* CAM sys_mclk */
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MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
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MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
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MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
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/* SPI1 cs */
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MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
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>;
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};
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
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MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
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MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
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/* SPI2 cs */
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MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
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>;
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};
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
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MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
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MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
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MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
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MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
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MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
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MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
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MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
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MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
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MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
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MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
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MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
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/* Ethernet PHY reset */
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MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
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/* Ethernet PHY interrupt */
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MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
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MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
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MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
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>;
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};
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pinctrl_gpio_bl_on: gpioblon {
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fsl,pins = <
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MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
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>;
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};
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pinctrl_gpio_keys: gpio1io04grp {
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fsl,pins = <
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/* Power button */
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MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
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>;
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};
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pinctrl_hdmi_cec: hdmicecgrp {
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fsl,pins = <
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MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
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>;
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};
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pinctrl_hdmi_ddc: hdmiddcgrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
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MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
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MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c3_recovery: i2c3recoverygrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
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MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
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>;
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};
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pinctrl_ipu1_lcdif: ipu1lcdifgrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61
|
|
/* DE */
|
|
MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61
|
|
/* HSync */
|
|
MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61
|
|
/* VSync */
|
|
MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61
|
|
MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61
|
|
MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61
|
|
MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61
|
|
MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61
|
|
MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61
|
|
MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61
|
|
MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61
|
|
MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61
|
|
MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61
|
|
MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61
|
|
MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61
|
|
MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61
|
|
MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61
|
|
MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61
|
|
MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61
|
|
MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61
|
|
MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61
|
|
MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61
|
|
MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61
|
|
MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61
|
|
MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61
|
|
MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61
|
|
MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61
|
|
MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61
|
|
>;
|
|
};
|
|
|
|
pinctrl_ipu2_vdac: ipu2vdacgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
|
|
MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1
|
|
MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1
|
|
MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1
|
|
MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9
|
|
MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9
|
|
MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9
|
|
MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9
|
|
MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9
|
|
MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9
|
|
MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9
|
|
MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9
|
|
MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9
|
|
MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9
|
|
MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9
|
|
MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9
|
|
MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9
|
|
MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9
|
|
MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9
|
|
MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9
|
|
>;
|
|
};
|
|
|
|
pinctrl_mmc_cd: gpiommccdgrp {
|
|
fsl,pins = <
|
|
/* MMC1 CD */
|
|
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm1: pwm1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm2: pwm2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm3: pwm3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm4: pwm4grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
|
|
fsl,pins = <
|
|
/* USBH_EN */
|
|
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
|
|
>;
|
|
};
|
|
|
|
pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
|
|
fsl,pins = <
|
|
/* USBH_HUB_EN */
|
|
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
|
|
>;
|
|
};
|
|
|
|
pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
|
|
fsl,pins = <
|
|
/* USBO1 power en */
|
|
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
|
|
>;
|
|
};
|
|
|
|
pinctrl_reset_moci: gpioresetmocigrp {
|
|
fsl,pins = <
|
|
/* RESET_MOCI control */
|
|
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
|
|
>;
|
|
};
|
|
|
|
pinctrl_sd_cd: gpiosdcdgrp {
|
|
fsl,pins = <
|
|
/* SD1 CD */
|
|
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_spdif: spdifgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
|
|
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_touch_int: gpiotouchintgrp {
|
|
fsl,pins = <
|
|
/* STMPE811 interrupt */
|
|
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1_dce: uart1dcegrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
/* DTE mode */
|
|
pinctrl_uart1_dte: uart1dtegrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
|
|
MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
/* Additional DTR, DSR, DCD */
|
|
pinctrl_uart1_ctrl: uart1ctrlgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
|
|
MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
|
|
MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2_dce: uart2dcegrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
/* DTE mode */
|
|
pinctrl_uart2_dte: uart2dtegrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
|
|
MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart4_dce: uart4dcegrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
/* DTE mode */
|
|
pinctrl_uart4_dte: uart4dtegrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5_dce: uart5dcegrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
/* DTE mode */
|
|
pinctrl_uart5_dte: uart5dtegrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg: usbotggrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_4bit: usdhc1grp_4bit {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
|
|
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
|
|
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
|
|
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
|
|
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
|
|
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_8bit: usdhc1grp_8bit {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
|
|
MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
|
|
MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
|
|
MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
|
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
|
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
|
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
|
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
|
/* eMMC reset */
|
|
MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
|
|
>;
|
|
};
|
|
};
|