44 lines
		
	
	
		
			1.0 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			44 lines
		
	
	
		
			1.0 KiB
		
	
	
	
		
			C
		
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /*
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|  * (C) Copyright 2000-2004
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|  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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|  */
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| 
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| #include <common.h>
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| #include <clock_legacy.h>
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| #include <mpc8xx.h>
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| #include <asm/processor.h>
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| #include <asm/io.h>
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| 
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| DECLARE_GLOBAL_DATA_PTR;
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| 
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| /*
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|  * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
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|  */
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| int get_clocks(void)
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| {
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| 	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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| 	uint sccr = in_be32(&immap->im_clkrst.car_sccr);
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| 	uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2);
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| 
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| 	/*
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| 	 * If for some reason measuring the gclk frequency won't
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| 	 * work, we return the hardwired value.
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| 	 * (For example, the cogent CMA286-60 CPU module has no
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| 	 * separate oscillator for PITRTCLK)
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| 	 */
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| 	gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
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| 
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| 	if ((sccr & SCCR_EBDF11) == 0) {
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| 		/* No Bus Divider active */
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| 		gd->bus_clk = gd->cpu_clk;
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| 	} else {
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| 		/* The MPC8xx has only one BDF: half clock speed */
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| 		gd->bus_clk = gd->cpu_clk / 2;
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| 	}
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| 
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| 	gd->arch.brg_clk = gd->cpu_clk / divider;
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| 
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| 	return 0;
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| }
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