442 lines
16 KiB
C
442 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright Altera Corporation (C) 2014-2015
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*/
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#ifndef _SOCFPGA_SDRAM_GEN5_H_
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#define _SOCFPGA_SDRAM_GEN5_H_
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#ifndef __ASSEMBLY__
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unsigned long sdram_calculate_size(void);
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int sdram_mmr_init_full(unsigned int sdr_phy_reg);
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int sdram_calibration_full(void);
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const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
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void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
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void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
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const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
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const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
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const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
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#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
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struct socfpga_sdr_ctrl {
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u32 ctrl_cfg;
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u32 dram_timing1;
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u32 dram_timing2;
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u32 dram_timing3;
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u32 dram_timing4; /* 0x10 */
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u32 lowpwr_timing;
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u32 dram_odt;
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u32 extratime1;
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u32 __padding0[3];
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u32 dram_addrw; /* 0x2c */
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u32 dram_if_width; /* 0x30 */
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u32 dram_dev_width;
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u32 dram_sts;
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u32 dram_intr;
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u32 sbe_count; /* 0x40 */
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u32 dbe_count;
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u32 err_addr;
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u32 drop_count;
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u32 drop_addr; /* 0x50 */
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u32 lowpwr_eq;
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u32 lowpwr_ack;
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u32 static_cfg;
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u32 ctrl_width; /* 0x60 */
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u32 cport_width;
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u32 cport_wmap;
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u32 cport_rmap;
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u32 rfifo_cmap; /* 0x70 */
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u32 wfifo_cmap;
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u32 cport_rdwr;
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u32 port_cfg;
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u32 fpgaport_rst; /* 0x80 */
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u32 __padding1;
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u32 fifo_cfg;
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u32 protport_default;
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u32 prot_rule_addr; /* 0x90 */
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u32 prot_rule_id;
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u32 prot_rule_data;
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u32 prot_rule_rdwr;
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u32 __padding2[3];
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u32 mp_priority; /* 0xac */
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u32 mp_weight0; /* 0xb0 */
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u32 mp_weight1;
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u32 mp_weight2;
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u32 mp_weight3;
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u32 mp_pacing0; /* 0xc0 */
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u32 mp_pacing1;
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u32 mp_pacing2;
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u32 mp_pacing3;
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u32 mp_threshold0; /* 0xd0 */
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u32 mp_threshold1;
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u32 mp_threshold2;
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u32 __padding3[29];
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u32 phy_ctrl0; /* 0x150 */
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u32 phy_ctrl1;
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u32 phy_ctrl2;
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};
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/* SDRAM configuration structure for the SPL. */
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struct socfpga_sdram_config {
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u32 ctrl_cfg;
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u32 dram_timing1;
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u32 dram_timing2;
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u32 dram_timing3;
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u32 dram_timing4;
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u32 lowpwr_timing;
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u32 dram_odt;
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u32 extratime1;
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u32 dram_addrw;
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u32 dram_if_width;
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u32 dram_dev_width;
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u32 dram_intr;
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u32 lowpwr_eq;
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u32 static_cfg;
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u32 ctrl_width;
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u32 cport_width;
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u32 cport_wmap;
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u32 cport_rmap;
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u32 rfifo_cmap;
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u32 wfifo_cmap;
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u32 cport_rdwr;
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u32 port_cfg;
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u32 fpgaport_rst;
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u32 fifo_cfg;
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u32 mp_priority;
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u32 mp_weight0;
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u32 mp_weight1;
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u32 mp_weight2;
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u32 mp_weight3;
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u32 mp_pacing0;
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u32 mp_pacing1;
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u32 mp_pacing2;
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u32 mp_pacing3;
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u32 mp_threshold0;
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u32 mp_threshold1;
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u32 mp_threshold2;
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u32 phy_ctrl0;
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};
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struct socfpga_sdram_rw_mgr_config {
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u8 activate_0_and_1;
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u8 activate_0_and_1_wait1;
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u8 activate_0_and_1_wait2;
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u8 activate_1;
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u8 clear_dqs_enable;
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u8 guaranteed_read;
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u8 guaranteed_read_cont;
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u8 guaranteed_write;
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u8 guaranteed_write_wait0;
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u8 guaranteed_write_wait1;
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u8 guaranteed_write_wait2;
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u8 guaranteed_write_wait3;
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u8 idle;
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u8 idle_loop1;
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u8 idle_loop2;
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u8 init_reset_0_cke_0;
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u8 init_reset_1_cke_0;
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u8 lfsr_wr_rd_bank_0;
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u8 lfsr_wr_rd_bank_0_data;
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u8 lfsr_wr_rd_bank_0_dqs;
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u8 lfsr_wr_rd_bank_0_nop;
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u8 lfsr_wr_rd_bank_0_wait;
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u8 lfsr_wr_rd_bank_0_wl_1;
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u8 lfsr_wr_rd_dm_bank_0;
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u8 lfsr_wr_rd_dm_bank_0_data;
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u8 lfsr_wr_rd_dm_bank_0_dqs;
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u8 lfsr_wr_rd_dm_bank_0_nop;
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u8 lfsr_wr_rd_dm_bank_0_wait;
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u8 lfsr_wr_rd_dm_bank_0_wl_1;
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u8 mrs0_dll_reset;
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u8 mrs0_dll_reset_mirr;
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u8 mrs0_user;
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u8 mrs0_user_mirr;
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u8 mrs1;
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u8 mrs1_mirr;
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u8 mrs2;
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u8 mrs2_mirr;
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u8 mrs3;
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u8 mrs3_mirr;
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u8 precharge_all;
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u8 read_b2b;
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u8 read_b2b_wait1;
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u8 read_b2b_wait2;
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u8 refresh_all;
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u8 rreturn;
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u8 sgle_read;
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u8 zqcl;
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u8 true_mem_data_mask_width;
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u8 mem_address_mirroring;
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u8 mem_data_mask_width;
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u8 mem_data_width;
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u8 mem_dq_per_read_dqs;
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u8 mem_dq_per_write_dqs;
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u8 mem_if_read_dqs_width;
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u8 mem_if_write_dqs_width;
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u8 mem_number_of_cs_per_dimm;
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u8 mem_number_of_ranks;
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u8 mem_virtual_groups_per_read_dqs;
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u8 mem_virtual_groups_per_write_dqs;
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};
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struct socfpga_sdram_io_config {
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u16 delay_per_opa_tap;
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u8 delay_per_dchain_tap;
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u8 delay_per_dqs_en_dchain_tap;
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u8 dll_chain_length;
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u8 dqdqs_out_phase_max;
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u8 dqs_en_delay_max;
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u8 dqs_en_delay_offset;
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u8 dqs_en_phase_max;
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u8 dqs_in_delay_max;
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u8 dqs_in_reserve;
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u8 dqs_out_reserve;
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u8 io_in_delay_max;
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u8 io_out1_delay_max;
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u8 io_out2_delay_max;
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u8 shift_dqs_en_when_shift_dqs;
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};
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struct socfpga_sdram_misc_config {
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u32 reg_file_init_seq_signature;
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u8 afi_rate_ratio;
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u8 calib_lfifo_offset;
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u8 calib_vfifo_offset;
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u8 enable_super_quick_calibration;
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u8 max_latency_count_width;
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u8 read_valid_fifo_size;
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u8 tinit_cntr0_val;
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u8 tinit_cntr1_val;
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u8 tinit_cntr2_val;
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u8 treset_cntr0_val;
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u8 treset_cntr1_val;
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u8 treset_cntr2_val;
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};
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#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
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#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
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#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
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#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
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#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
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#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
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#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
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#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
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#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
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#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
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#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
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#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
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#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
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#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
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#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
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#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
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#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
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#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
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/* Register template: sdr::ctrlgrp::dramtiming1 */
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#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
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#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
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#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
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#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
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#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
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#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
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#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
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#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
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#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
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#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
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#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
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#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
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/* Register template: sdr::ctrlgrp::dramtiming2 */
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#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
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#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
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#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
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#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
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#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
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#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
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#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
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#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
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#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
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#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
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/* Register template: sdr::ctrlgrp::dramtiming3 */
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#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
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#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
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#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
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#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
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#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
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#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
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#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
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#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
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#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
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#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
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/* Register template: sdr::ctrlgrp::dramtiming4 */
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#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
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#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
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#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
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#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
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#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
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#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
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/* Register template: sdr::ctrlgrp::lowpwrtiming */
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#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
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#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
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#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
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#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
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/* Register template: sdr::ctrlgrp::dramaddrw */
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#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
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#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
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#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
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#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
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#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
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#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
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#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
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#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
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/* Register template: sdr::ctrlgrp::dramifwidth */
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#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
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#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
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/* Register template: sdr::ctrlgrp::dramdevwidth */
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#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
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#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
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/* Register template: sdr::ctrlgrp::dramintr */
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#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
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#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
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#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
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#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
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/* Register template: sdr::ctrlgrp::staticcfg */
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#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
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#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
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#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
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#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
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#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
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#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
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/* Register template: sdr::ctrlgrp::ctrlwidth */
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#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
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#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
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/* Register template: sdr::ctrlgrp::cportwidth */
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#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
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#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
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/* Register template: sdr::ctrlgrp::cportwmap */
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#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
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#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
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/* Register template: sdr::ctrlgrp::cportrmap */
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#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
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#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
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/* Register template: sdr::ctrlgrp::rfifocmap */
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#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
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#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
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/* Register template: sdr::ctrlgrp::wfifocmap */
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#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
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#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
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/* Register template: sdr::ctrlgrp::cportrdwr */
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#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
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#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
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/* Register template: sdr::ctrlgrp::portcfg */
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#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
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#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
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#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
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#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
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/* Register template: sdr::ctrlgrp::fifocfg */
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#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
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#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
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#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
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#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
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/* Register template: sdr::ctrlgrp::mppriority */
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#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
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#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
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#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
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#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
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#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
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/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
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0xffffffff
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/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
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0xffffffff
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/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
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0x0000ffff
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/* Register template: sdr::ctrlgrp::remappriority */
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#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
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#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
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/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
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(((x) << 12) & 0xfffff000)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
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(((x) << 10) & 0x00000c00)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
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(((x) << 6) & 0x000000c0)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
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(((x) << 8) & 0x00000100)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
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(((x) << 9) & 0x00000200)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
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(((x) << 4) & 0x00000030)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
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(((x) << 2) & 0x0000000c)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
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(((x) << 0) & 0x00000003)
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/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
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(((x) << 12) & 0xfffff000)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
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(((x) << 0) & 0x00000fff)
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/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
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(((x) << 0) & 0x00000fff)
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/* Register template: sdr::ctrlgrp::dramodt */
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#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
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#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
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#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
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#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
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/* Field instance: sdr::ctrlgrp::dramsts */
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#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
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#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
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/* Register template: sdr::ctrlgrp::extratime1 */
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#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
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#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
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#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
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/* SDRAM width macro for configuration with ECC */
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#define SDRAM_WIDTH_32BIT_WITH_ECC 40
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#define SDRAM_WIDTH_16BIT_WITH_ECC 24
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#endif
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#endif /* _SOCFPGA_SDRAM_GEN5_H_ */
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