150 lines
3.2 KiB
Plaintext
150 lines
3.2 KiB
Plaintext
/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "andestech,ax25";
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model = "andestech,ax25";
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aliases {
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uart0 = &serial0;
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spi0 = &spi;
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} ;
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chosen {
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bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
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stdout-path = "uart0:38400n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <10000000>;
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CPU0: cpu@0 {
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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clock-frequency = <60000000>;
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CPU0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x00000000 0x0 0x40000000>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "andestech,riscv-ae350-soc";
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ranges;
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};
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plmt0@e6000000 {
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compatible = "riscv,plmt0";
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interrupts-extended = <&CPU0_intc 7>;
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reg = <0x0 0xe6000000 0x0 0x100000>;
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};
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plic0: interrupt-controller@e4000000 {
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compatible = "riscv,plic0";
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#address-cells = <2>;
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0x0 0xe4000000 0x0 0x2000000>;
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riscv,ndev=<31>;
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interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
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};
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plic1: interrupt-controller@e6400000 {
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compatible = "riscv,plic1";
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#address-cells = <2>;
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0x0 0xe6400000 0x0 0x400000>;
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riscv,ndev=<1>;
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interrupts-extended = <&CPU0_intc 3>;
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};
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spiclk: virt_100mhz {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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timer0: timer@f0400000 {
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compatible = "andestech,atcpit100";
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reg = <0x0 0xf0400000 0x0 0x1000>;
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clock-frequency = <40000000>;
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interrupts = <3 4>;
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interrupt-parent = <&plic0>;
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};
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serial0: serial@f0300000 {
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compatible = "andestech,uart16550", "ns16550a";
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reg = <0x0 0xf0300000 0x0 0x1000>;
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interrupts = <9 4>;
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clock-frequency = <19660800>;
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reg-shift = <2>;
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reg-offset = <32>;
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no-loopback-test = <1>;
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interrupt-parent = <&plic0>;
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};
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mac0: mac@e0100000 {
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compatible = "andestech,atmac100";
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reg = <0x0 0xe0100000 0x0 0x1000>;
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interrupts = <19 4>;
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interrupt-parent = <&plic0>;
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};
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mmc0: mmc@f0e00000 {
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compatible = "andestech,atfsdc010";
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max-frequency = <100000000>;
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clock-freq-min-max = <400000 100000000>;
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fifo-depth = <0x10>;
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reg = <0x0 0xf0e00000 0x0 0x1000>;
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interrupts = <18 4>;
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cap-sd-highspeed;
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interrupt-parent = <&plic0>;
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};
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smc0: smc@e0400000 {
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compatible = "andestech,atfsmc020";
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reg = <0x0 0xe0400000 0x0 0x1000>;
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};
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nor@0,0 {
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compatible = "cfi-flash";
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reg = <0x0 0x88000000 0x0 0x1000>;
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bank-width = <2>;
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device-width = <1>;
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};
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spi: spi@f0b00000 {
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compatible = "andestech,atcspi200";
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reg = <0x0 0xf0b00000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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clocks = <&spiclk>;
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interrupts = <3 4>;
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interrupt-parent = <&plic0>;
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flash@0 {
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compatible = "spi-flash";
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spi-max-frequency = <50000000>;
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reg = <0>;
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spi-cpol;
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spi-cpha;
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};
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};
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};
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