304 lines
6.4 KiB
Plaintext
304 lines
6.4 KiB
Plaintext
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset-controller/stm32mp1-resets.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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aliases {
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serial3 = &uart4;
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};
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intc: interrupt-controller@a0021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xa0021000 0x1000>,
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<0xa0022000 0x2000>;
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_csi: clk-csi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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uart4: serial@40010000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40010000 0x400>;
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clocks = <&rcc_clk UART4_K>;
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status = "disabled";
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};
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rcc: rcc@50000000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x50000000 0x1000>;
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rcc_clk: rcc-clk@50000000 {
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#clock-cells = <1>;
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compatible = "st,stm32mp1-rcc-clk";
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};
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rcc_rst: rcc-reset@50000000 {
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#reset-cells = <1>;
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compatible = "st,stm32mp1-rcc-rst";
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};
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};
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pinctrl: pin-controller {
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compatible = "st,stm32mp157-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x50002000 0xa400>;
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pins-are-numbered;
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gpioa: gpio@50002000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc_clk GPIOA>;
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st,bank-name = "GPIOA";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 0 16>;
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status = "disabled";
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};
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gpiob: gpio@50003000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&rcc_clk GPIOB>;
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st,bank-name = "GPIOB";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 16 16>;
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status = "disabled";
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};
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gpioc: gpio@50004000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&rcc_clk GPIOC>;
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st,bank-name = "GPIOC";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 32 16>;
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status = "disabled";
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};
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gpiod: gpio@50005000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x400>;
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clocks = <&rcc_clk GPIOD>;
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st,bank-name = "GPIOD";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 48 16>;
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status = "disabled";
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};
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gpioe: gpio@50006000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x400>;
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clocks = <&rcc_clk GPIOE>;
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st,bank-name = "GPIOE";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 64 16>;
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status = "disabled";
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};
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gpiof: gpio@50007000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000 0x400>;
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clocks = <&rcc_clk GPIOF>;
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st,bank-name = "GPIOF";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 80 16>;
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status = "disabled";
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};
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gpiog: gpio@50008000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x6000 0x400>;
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clocks = <&rcc_clk GPIOG>;
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st,bank-name = "GPIOG";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 96 16>;
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status = "disabled";
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};
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gpioh: gpio@50009000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x7000 0x400>;
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clocks = <&rcc_clk GPIOH>;
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st,bank-name = "GPIOH";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 112 16>;
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status = "disabled";
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};
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gpioi: gpio@5000a000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x8000 0x400>;
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clocks = <&rcc_clk GPIOI>;
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st,bank-name = "GPIOI";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 128 16>;
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status = "disabled";
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};
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gpioj: gpio@5000b000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x9000 0x400>;
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clocks = <&rcc_clk GPIOJ>;
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st,bank-name = "GPIOJ";
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ngpios = <16>;
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gpio-ranges = <&pinctrl 0 144 16>;
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status = "disabled";
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};
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gpiok: gpio@5000c000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xa000 0x400>;
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clocks = <&rcc_clk GPIOK>;
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st,bank-name = "GPIOK";
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ngpios = <8>;
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gpio-ranges = <&pinctrl 0 160 8>;
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status = "disabled";
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};
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};
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pinctrl_z: pin-controller-z {
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compatible = "st,stm32mp157-z-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x54004000 0x400>;
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pins-are-numbered;
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gpioz: gpio@54004000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x400>;
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clocks = <&rcc_clk GPIOZ>;
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st,bank-name = "GPIOZ";
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st,bank-ioport = <11>;
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ngpios = <8>;
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gpio-ranges = <&pinctrl_z 0 400 8>;
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status = "disabled";
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};
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};
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sdmmc1: sdmmc@58005000 {
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compatible = "st,stm32-sdmmc2";
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reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
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reg-names = "sdmmc", "delay";
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clocks = <&rcc_clk SDMMC1_K>;
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resets = <&rcc_rst SDMMC1_R>;
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st,idma = <1>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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status = "disabled";
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};
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i2c4: i2c@5c002000 {
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compatible = "st,stm32f7-i2c";
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reg = <0x5c002000 0x400>;
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interrupt-names = "event", "error", "wakeup";
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clocks = <&rcc_clk I2C4_K>;
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resets = <&rcc_rst I2C4_R>;
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#address-cells = <1>;
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#size-cells = <0>;
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wakeup-source;
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status = "disabled";
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};
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};
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};
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