649 lines
14 KiB
C
649 lines
14 KiB
C
/*
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* Copyright (C) 2017 NXP Semiconductors
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* Copyright (C) 2017 Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DRIVER_NVME_H__
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#define __DRIVER_NVME_H__
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#include <asm/io.h>
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struct nvme_id_power_state {
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__le16 max_power; /* centiwatts */
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__u8 rsvd2;
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__u8 flags;
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__le32 entry_lat; /* microseconds */
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__le32 exit_lat; /* microseconds */
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__u8 read_tput;
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__u8 read_lat;
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__u8 write_tput;
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__u8 write_lat;
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__le16 idle_power;
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__u8 idle_scale;
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__u8 rsvd19;
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__le16 active_power;
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__u8 active_work_scale;
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__u8 rsvd23[9];
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};
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enum {
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NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
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NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
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};
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struct nvme_id_ctrl {
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__le16 vid;
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__le16 ssvid;
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char sn[20];
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char mn[40];
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char fr[8];
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__u8 rab;
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__u8 ieee[3];
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__u8 mic;
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__u8 mdts;
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__u16 cntlid;
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__u32 ver;
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__u8 rsvd84[172];
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__le16 oacs;
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__u8 acl;
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__u8 aerl;
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__u8 frmw;
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__u8 lpa;
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__u8 elpe;
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__u8 npss;
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__u8 avscc;
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__u8 apsta;
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__le16 wctemp;
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__le16 cctemp;
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__u8 rsvd270[242];
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__u8 sqes;
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__u8 cqes;
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__u8 rsvd514[2];
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__le32 nn;
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__le16 oncs;
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__le16 fuses;
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__u8 fna;
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__u8 vwc;
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__le16 awun;
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__le16 awupf;
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__u8 nvscc;
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__u8 rsvd531;
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__le16 acwu;
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__u8 rsvd534[2];
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__le32 sgls;
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__u8 rsvd540[1508];
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struct nvme_id_power_state psd[32];
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__u8 vs[1024];
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};
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enum {
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NVME_CTRL_ONCS_COMPARE = 1 << 0,
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NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
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NVME_CTRL_ONCS_DSM = 1 << 2,
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NVME_CTRL_VWC_PRESENT = 1 << 0,
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};
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struct nvme_lbaf {
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__le16 ms;
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__u8 ds;
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__u8 rp;
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};
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struct nvme_id_ns {
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__le64 nsze;
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__le64 ncap;
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__le64 nuse;
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__u8 nsfeat;
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__u8 nlbaf;
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__u8 flbas;
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__u8 mc;
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__u8 dpc;
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__u8 dps;
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__u8 nmic;
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__u8 rescap;
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__u8 fpi;
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__u8 rsvd33;
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__le16 nawun;
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__le16 nawupf;
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__le16 nacwu;
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__le16 nabsn;
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__le16 nabo;
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__le16 nabspf;
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__u16 rsvd46;
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__le64 nvmcap[2];
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__u8 rsvd64[40];
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__u8 nguid[16];
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__u8 eui64[8];
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struct nvme_lbaf lbaf[16];
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__u8 rsvd192[192];
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__u8 vs[3712];
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};
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enum {
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NVME_NS_FEAT_THIN = 1 << 0,
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NVME_NS_FLBAS_LBA_MASK = 0xf,
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NVME_NS_FLBAS_META_EXT = 0x10,
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NVME_LBAF_RP_BEST = 0,
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NVME_LBAF_RP_BETTER = 1,
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NVME_LBAF_RP_GOOD = 2,
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NVME_LBAF_RP_DEGRADED = 3,
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NVME_NS_DPC_PI_LAST = 1 << 4,
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NVME_NS_DPC_PI_FIRST = 1 << 3,
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NVME_NS_DPC_PI_TYPE3 = 1 << 2,
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NVME_NS_DPC_PI_TYPE2 = 1 << 1,
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NVME_NS_DPC_PI_TYPE1 = 1 << 0,
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NVME_NS_DPS_PI_FIRST = 1 << 3,
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NVME_NS_DPS_PI_MASK = 0x7,
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NVME_NS_DPS_PI_TYPE1 = 1,
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NVME_NS_DPS_PI_TYPE2 = 2,
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NVME_NS_DPS_PI_TYPE3 = 3,
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};
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struct nvme_smart_log {
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__u8 critical_warning;
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__u8 temperature[2];
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__u8 avail_spare;
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__u8 spare_thresh;
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__u8 percent_used;
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__u8 rsvd6[26];
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__u8 data_units_read[16];
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__u8 data_units_written[16];
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__u8 host_reads[16];
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__u8 host_writes[16];
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__u8 ctrl_busy_time[16];
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__u8 power_cycles[16];
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__u8 power_on_hours[16];
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__u8 unsafe_shutdowns[16];
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__u8 media_errors[16];
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__u8 num_err_log_entries[16];
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__le32 warning_temp_time;
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__le32 critical_comp_time;
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__le16 temp_sensor[8];
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__u8 rsvd216[296];
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};
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enum {
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NVME_SMART_CRIT_SPARE = 1 << 0,
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NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
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NVME_SMART_CRIT_RELIABILITY = 1 << 2,
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NVME_SMART_CRIT_MEDIA = 1 << 3,
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NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
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};
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struct nvme_lba_range_type {
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__u8 type;
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__u8 attributes;
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__u8 rsvd2[14];
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__u64 slba;
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__u64 nlb;
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__u8 guid[16];
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__u8 rsvd48[16];
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};
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enum {
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NVME_LBART_TYPE_FS = 0x01,
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NVME_LBART_TYPE_RAID = 0x02,
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NVME_LBART_TYPE_CACHE = 0x03,
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NVME_LBART_TYPE_SWAP = 0x04,
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NVME_LBART_ATTRIB_TEMP = 1 << 0,
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NVME_LBART_ATTRIB_HIDE = 1 << 1,
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};
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struct nvme_reservation_status {
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__le32 gen;
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__u8 rtype;
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__u8 regctl[2];
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__u8 resv5[2];
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__u8 ptpls;
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__u8 resv10[13];
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struct {
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__le16 cntlid;
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__u8 rcsts;
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__u8 resv3[5];
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__le64 hostid;
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__le64 rkey;
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} regctl_ds[];
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};
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/* I/O commands */
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enum nvme_opcode {
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nvme_cmd_flush = 0x00,
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nvme_cmd_write = 0x01,
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nvme_cmd_read = 0x02,
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nvme_cmd_write_uncor = 0x04,
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nvme_cmd_compare = 0x05,
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nvme_cmd_write_zeroes = 0x08,
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nvme_cmd_dsm = 0x09,
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nvme_cmd_resv_register = 0x0d,
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nvme_cmd_resv_report = 0x0e,
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nvme_cmd_resv_acquire = 0x11,
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nvme_cmd_resv_release = 0x15,
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};
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struct nvme_common_command {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__le32 cdw2[2];
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__le64 metadata;
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__le64 prp1;
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__le64 prp2;
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__le32 cdw10[6];
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};
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struct nvme_rw_command {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd2;
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__le64 metadata;
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__le64 prp1;
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__le64 prp2;
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__le64 slba;
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__le16 length;
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__le16 control;
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__le32 dsmgmt;
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__le32 reftag;
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__le16 apptag;
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__le16 appmask;
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};
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enum {
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NVME_RW_LR = 1 << 15,
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NVME_RW_FUA = 1 << 14,
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NVME_RW_DSM_FREQ_UNSPEC = 0,
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NVME_RW_DSM_FREQ_TYPICAL = 1,
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NVME_RW_DSM_FREQ_RARE = 2,
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NVME_RW_DSM_FREQ_READS = 3,
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NVME_RW_DSM_FREQ_WRITES = 4,
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NVME_RW_DSM_FREQ_RW = 5,
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NVME_RW_DSM_FREQ_ONCE = 6,
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NVME_RW_DSM_FREQ_PREFETCH = 7,
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NVME_RW_DSM_FREQ_TEMP = 8,
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NVME_RW_DSM_LATENCY_NONE = 0 << 4,
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NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
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NVME_RW_DSM_LATENCY_NORM = 2 << 4,
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NVME_RW_DSM_LATENCY_LOW = 3 << 4,
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NVME_RW_DSM_SEQ_REQ = 1 << 6,
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NVME_RW_DSM_COMPRESSED = 1 << 7,
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NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
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NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
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NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
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NVME_RW_PRINFO_PRACT = 1 << 13,
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};
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struct nvme_dsm_cmd {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd2[2];
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__le64 prp1;
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__le64 prp2;
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__le32 nr;
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__le32 attributes;
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__u32 rsvd12[4];
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};
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enum {
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NVME_DSMGMT_IDR = 1 << 0,
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NVME_DSMGMT_IDW = 1 << 1,
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NVME_DSMGMT_AD = 1 << 2,
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};
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struct nvme_dsm_range {
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__le32 cattr;
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__le32 nlb;
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__le64 slba;
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};
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/* Admin commands */
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enum nvme_admin_opcode {
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nvme_admin_delete_sq = 0x00,
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nvme_admin_create_sq = 0x01,
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nvme_admin_get_log_page = 0x02,
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nvme_admin_delete_cq = 0x04,
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nvme_admin_create_cq = 0x05,
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nvme_admin_identify = 0x06,
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nvme_admin_abort_cmd = 0x08,
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nvme_admin_set_features = 0x09,
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nvme_admin_get_features = 0x0a,
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nvme_admin_async_event = 0x0c,
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nvme_admin_activate_fw = 0x10,
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nvme_admin_download_fw = 0x11,
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nvme_admin_format_nvm = 0x80,
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nvme_admin_security_send = 0x81,
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nvme_admin_security_recv = 0x82,
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};
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enum {
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NVME_QUEUE_PHYS_CONTIG = (1 << 0),
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NVME_CQ_IRQ_ENABLED = (1 << 1),
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NVME_SQ_PRIO_URGENT = (0 << 1),
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NVME_SQ_PRIO_HIGH = (1 << 1),
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NVME_SQ_PRIO_MEDIUM = (2 << 1),
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NVME_SQ_PRIO_LOW = (3 << 1),
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NVME_FEAT_ARBITRATION = 0x01,
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NVME_FEAT_POWER_MGMT = 0x02,
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NVME_FEAT_LBA_RANGE = 0x03,
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NVME_FEAT_TEMP_THRESH = 0x04,
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NVME_FEAT_ERR_RECOVERY = 0x05,
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NVME_FEAT_VOLATILE_WC = 0x06,
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NVME_FEAT_NUM_QUEUES = 0x07,
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NVME_FEAT_IRQ_COALESCE = 0x08,
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NVME_FEAT_IRQ_CONFIG = 0x09,
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NVME_FEAT_WRITE_ATOMIC = 0x0a,
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NVME_FEAT_ASYNC_EVENT = 0x0b,
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NVME_FEAT_AUTO_PST = 0x0c,
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NVME_FEAT_SW_PROGRESS = 0x80,
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NVME_FEAT_HOST_ID = 0x81,
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NVME_FEAT_RESV_MASK = 0x82,
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NVME_FEAT_RESV_PERSIST = 0x83,
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NVME_LOG_ERROR = 0x01,
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NVME_LOG_SMART = 0x02,
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NVME_LOG_FW_SLOT = 0x03,
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NVME_LOG_RESERVATION = 0x80,
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NVME_FWACT_REPL = (0 << 3),
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NVME_FWACT_REPL_ACTV = (1 << 3),
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NVME_FWACT_ACTV = (2 << 3),
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};
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struct nvme_identify {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd2[2];
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__le64 prp1;
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__le64 prp2;
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__le32 cns;
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__u32 rsvd11[5];
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};
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struct nvme_features {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd2[2];
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__le64 prp1;
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__le64 prp2;
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__le32 fid;
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__le32 dword11;
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__u32 rsvd12[4];
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};
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struct nvme_create_cq {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__u32 rsvd1[5];
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__le64 prp1;
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__u64 rsvd8;
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__le16 cqid;
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__le16 qsize;
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__le16 cq_flags;
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__le16 irq_vector;
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__u32 rsvd12[4];
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};
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struct nvme_create_sq {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__u32 rsvd1[5];
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__le64 prp1;
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__u64 rsvd8;
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__le16 sqid;
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__le16 qsize;
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__le16 sq_flags;
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__le16 cqid;
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__u32 rsvd12[4];
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};
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struct nvme_delete_queue {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__u32 rsvd1[9];
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__le16 qid;
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__u16 rsvd10;
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__u32 rsvd11[5];
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};
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struct nvme_abort_cmd {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__u32 rsvd1[9];
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__le16 sqid;
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__u16 cid;
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__u32 rsvd11[5];
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};
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struct nvme_download_firmware {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__u32 rsvd1[5];
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__le64 prp1;
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__le64 prp2;
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__le32 numd;
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__le32 offset;
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__u32 rsvd12[4];
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};
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struct nvme_format_cmd {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd2[4];
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__le32 cdw10;
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__u32 rsvd11[5];
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};
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struct nvme_command {
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union {
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struct nvme_common_command common;
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struct nvme_rw_command rw;
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struct nvme_identify identify;
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struct nvme_features features;
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struct nvme_create_cq create_cq;
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struct nvme_create_sq create_sq;
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struct nvme_delete_queue delete_queue;
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struct nvme_download_firmware dlfw;
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struct nvme_format_cmd format;
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struct nvme_dsm_cmd dsm;
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struct nvme_abort_cmd abort;
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};
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};
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enum {
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NVME_SC_SUCCESS = 0x0,
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NVME_SC_INVALID_OPCODE = 0x1,
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NVME_SC_INVALID_FIELD = 0x2,
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NVME_SC_CMDID_CONFLICT = 0x3,
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NVME_SC_DATA_XFER_ERROR = 0x4,
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NVME_SC_POWER_LOSS = 0x5,
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NVME_SC_INTERNAL = 0x6,
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NVME_SC_ABORT_REQ = 0x7,
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NVME_SC_ABORT_QUEUE = 0x8,
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NVME_SC_FUSED_FAIL = 0x9,
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NVME_SC_FUSED_MISSING = 0xa,
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NVME_SC_INVALID_NS = 0xb,
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NVME_SC_CMD_SEQ_ERROR = 0xc,
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NVME_SC_SGL_INVALID_LAST = 0xd,
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NVME_SC_SGL_INVALID_COUNT = 0xe,
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NVME_SC_SGL_INVALID_DATA = 0xf,
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NVME_SC_SGL_INVALID_METADATA = 0x10,
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NVME_SC_SGL_INVALID_TYPE = 0x11,
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NVME_SC_LBA_RANGE = 0x80,
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NVME_SC_CAP_EXCEEDED = 0x81,
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NVME_SC_NS_NOT_READY = 0x82,
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NVME_SC_RESERVATION_CONFLICT = 0x83,
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NVME_SC_CQ_INVALID = 0x100,
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NVME_SC_QID_INVALID = 0x101,
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NVME_SC_QUEUE_SIZE = 0x102,
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NVME_SC_ABORT_LIMIT = 0x103,
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NVME_SC_ABORT_MISSING = 0x104,
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NVME_SC_ASYNC_LIMIT = 0x105,
|
|
NVME_SC_FIRMWARE_SLOT = 0x106,
|
|
NVME_SC_FIRMWARE_IMAGE = 0x107,
|
|
NVME_SC_INVALID_VECTOR = 0x108,
|
|
NVME_SC_INVALID_LOG_PAGE = 0x109,
|
|
NVME_SC_INVALID_FORMAT = 0x10a,
|
|
NVME_SC_FIRMWARE_NEEDS_RESET = 0x10b,
|
|
NVME_SC_INVALID_QUEUE = 0x10c,
|
|
NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
|
|
NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
|
|
NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
|
|
NVME_SC_FW_NEEDS_RESET_SUBSYS = 0x110,
|
|
NVME_SC_BAD_ATTRIBUTES = 0x180,
|
|
NVME_SC_INVALID_PI = 0x181,
|
|
NVME_SC_READ_ONLY = 0x182,
|
|
NVME_SC_WRITE_FAULT = 0x280,
|
|
NVME_SC_READ_ERROR = 0x281,
|
|
NVME_SC_GUARD_CHECK = 0x282,
|
|
NVME_SC_APPTAG_CHECK = 0x283,
|
|
NVME_SC_REFTAG_CHECK = 0x284,
|
|
NVME_SC_COMPARE_FAILED = 0x285,
|
|
NVME_SC_ACCESS_DENIED = 0x286,
|
|
NVME_SC_DNR = 0x4000,
|
|
};
|
|
|
|
struct nvme_completion {
|
|
__le32 result; /* Used by admin commands to return data */
|
|
__u32 rsvd;
|
|
__le16 sq_head; /* how much of this queue may be reclaimed */
|
|
__le16 sq_id; /* submission queue that generated this entry */
|
|
__u16 command_id; /* of the command which completed */
|
|
__le16 status; /* did the command fail, and if so, why? */
|
|
};
|
|
|
|
/*
|
|
* Registers should always be accessed with double word or quad word
|
|
* accesses. Registers with 64-bit address pointers should be written
|
|
* to with dword accesses by writing the low dword first (ptr[0]),
|
|
* then the high dword (ptr[1]) second.
|
|
*/
|
|
static inline u64 nvme_readq(__le64 volatile *regs)
|
|
{
|
|
#if BITS_PER_LONG == 64
|
|
return readq(regs);
|
|
#else
|
|
__u32 *ptr = (__u32 *)regs;
|
|
u64 val_lo = readl(ptr);
|
|
u64 val_hi = readl(ptr + 1);
|
|
|
|
return val_lo + (val_hi << 32);
|
|
#endif
|
|
}
|
|
|
|
static inline void nvme_writeq(const u64 val, __le64 volatile *regs)
|
|
{
|
|
#if BITS_PER_LONG == 64
|
|
writeq(val, regs);
|
|
#else
|
|
__u32 *ptr = (__u32 *)regs;
|
|
u32 val_lo = lower_32_bits(val);
|
|
u32 val_hi = upper_32_bits(val);
|
|
writel(val_lo, ptr);
|
|
writel(val_hi, ptr + 1);
|
|
#endif
|
|
}
|
|
|
|
struct nvme_bar {
|
|
__u64 cap; /* Controller Capabilities */
|
|
__u32 vs; /* Version */
|
|
__u32 intms; /* Interrupt Mask Set */
|
|
__u32 intmc; /* Interrupt Mask Clear */
|
|
__u32 cc; /* Controller Configuration */
|
|
__u32 rsvd1; /* Reserved */
|
|
__u32 csts; /* Controller Status */
|
|
__u32 rsvd2; /* Reserved */
|
|
__u32 aqa; /* Admin Queue Attributes */
|
|
__u64 asq; /* Admin SQ Base Address */
|
|
__u64 acq; /* Admin CQ Base Address */
|
|
};
|
|
|
|
#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
|
|
#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
|
|
#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
|
|
#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
|
|
#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
|
|
|
|
#define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))
|
|
|
|
enum {
|
|
NVME_CC_ENABLE = 1 << 0,
|
|
NVME_CC_CSS_NVM = 0 << 4,
|
|
NVME_CC_MPS_SHIFT = 7,
|
|
NVME_CC_ARB_RR = 0 << 11,
|
|
NVME_CC_ARB_WRRU = 1 << 11,
|
|
NVME_CC_ARB_VS = 7 << 11,
|
|
NVME_CC_SHN_NONE = 0 << 14,
|
|
NVME_CC_SHN_NORMAL = 1 << 14,
|
|
NVME_CC_SHN_ABRUPT = 2 << 14,
|
|
NVME_CC_SHN_MASK = 3 << 14,
|
|
NVME_CC_IOSQES = 6 << 16,
|
|
NVME_CC_IOCQES = 4 << 20,
|
|
NVME_CSTS_RDY = 1 << 0,
|
|
NVME_CSTS_CFS = 1 << 1,
|
|
NVME_CSTS_SHST_NORMAL = 0 << 2,
|
|
NVME_CSTS_SHST_OCCUR = 1 << 2,
|
|
NVME_CSTS_SHST_CMPLT = 2 << 2,
|
|
NVME_CSTS_SHST_MASK = 3 << 2,
|
|
};
|
|
|
|
/* Represents an NVM Express device. Each nvme_dev is a PCI function. */
|
|
struct nvme_dev {
|
|
struct list_head node;
|
|
struct nvme_queue **queues;
|
|
u32 __iomem *dbs;
|
|
int instance;
|
|
unsigned queue_count;
|
|
unsigned online_queues;
|
|
unsigned max_qid;
|
|
int q_depth;
|
|
u32 db_stride;
|
|
u32 ctrl_config;
|
|
struct nvme_bar __iomem *bar;
|
|
struct list_head namespaces;
|
|
char serial[20];
|
|
char model[40];
|
|
char firmware_rev[8];
|
|
u32 max_transfer_shift;
|
|
u64 cap;
|
|
u32 stripe_size;
|
|
u32 page_size;
|
|
u8 vwc;
|
|
u64 *prp_pool;
|
|
u32 prp_entry_num;
|
|
u32 nn;
|
|
};
|
|
|
|
/*
|
|
* An NVM Express namespace is equivalent to a SCSI LUN.
|
|
* Each namespace is operated as an independent "device".
|
|
*/
|
|
struct nvme_ns {
|
|
struct list_head list;
|
|
struct nvme_dev *dev;
|
|
unsigned ns_id;
|
|
int devnum;
|
|
int lba_shift;
|
|
u8 flbas;
|
|
u64 mode_select_num_blocks;
|
|
u32 mode_select_block_len;
|
|
};
|
|
|
|
#endif /* __DRIVER_NVME_H__ */
|