152 lines
4.0 KiB
C
152 lines
4.0 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __DDR3_AXP_CONFIG_H
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#define __DDR3_AXP_CONFIG_H
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/*
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* DDR3_LOG_LEVEL Information
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*
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* Level 0: Provides an error code in a case of failure, RL, WL errors
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* and other algorithm failure
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* Level 1: Provides the D-Unit setup (SPD/Static configuration)
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* Level 2: Provides the windows margin as a results of DQS centeralization
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* Level 3: Provides the windows margin of each DQ as a results of DQS
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* centeralization
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*/
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#ifdef CONFIG_DDR_LOG_LEVEL
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#define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL
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#else
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#define DDR3_LOG_LEVEL 0
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#endif
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#define DDR3_PBS 1
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/* This flag allows the execution of SW WL/RL upon HW failure */
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#define DDR3_RUN_SW_WHEN_HW_FAIL 1
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/*
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* General Configurations
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*
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* The following parameters are required for proper setup:
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*
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* DDR_TARGET_FABRIC - Set desired fabric configuration
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* (for sample@Reset fabfreq parameter)
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* DRAM_ECC - Set ECC support 1/0
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* BUS_WIDTH - 64/32 bit
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* CONFIG_SPD_EEPROM - Enables auto detection of DIMMs and their timing values
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* DQS_CLK_ALIGNED - Set this if CLK and DQS signals are aligned on board
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* MIXED_DIMM_STATIC - Mixed DIMM + On board devices support (ODT registers
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* values are taken statically)
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* DDR3_TRAINING_DEBUG - Debug prints of internal code
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*/
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#define DDR_TARGET_FABRIC 5
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/* Only enable ECC if the board selects it */
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#ifdef CONFIG_BOARD_ECC_SUPPORT
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#define DRAM_ECC 1
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#else
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#define DRAM_ECC 0
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#endif
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#ifdef CONFIG_DDR_32BIT
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#define BUS_WIDTH 32
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#else
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#define BUS_WIDTH 64
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#endif
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#undef DQS_CLK_ALIGNED
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#undef MIXED_DIMM_STATIC
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#define DDR3_TRAINING_DEBUG 0
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#define REG_DIMM_SKIP_WL 0
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/* Marvell boards specific configurations */
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#if defined(DB_78X60_PCAC)
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#undef CONFIG_SPD_EEPROM
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#define STATIC_TRAINING
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#endif
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#if defined(DB_78X60_AMC)
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#undef CONFIG_SPD_EEPROM
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#undef DRAM_ECC
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#define DRAM_ECC 1
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#endif
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#ifdef CONFIG_SPD_EEPROM
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/*
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* DIMM support parameters:
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* DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T
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* DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs
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* (0xF=CS0+CS1+CS2+CS3, 0xC=CS2+CS3...)
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*/
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#define DRAM_2T 0x0
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#define DIMM_CS_BITMAP 0xF
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#define DUNIT_SPD
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#endif
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#ifdef DRAM_ECC
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/*
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* ECC support parameters:
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*
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* U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need
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* to configure the scrubbing area
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*/
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#define TRAINING_SIZE 0x20000
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#define U_BOOT_START_ADDR 0
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#define U_BOOT_SCRUB_SIZE 0x1000000 /* TRAINING_SIZE */
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#endif
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/*
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* Registered DIMM Support - In case registered DIMM is attached,
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* please supply the following values:
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* (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock
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* Driver with Parity and Quad Chip
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* Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications")
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* RC0: Global Features Control Word
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* RC1: Clock Driver Enable Control Word
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* RC2: Timing Control Word
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* RC3-RC5 - taken from SPD
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* RC8: Additional IBT Setting Control Word
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* RC9: Power Saving Settings Control Word
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* RC10: Encoding for RDIMM Operating Speed
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* RC11: Operating Voltage VDD and VREFCA Control Word
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*/
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#define RDIMM_RC0 0
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#define RDIMM_RC1 0
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#define RDIMM_RC2 0
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#define RDIMM_RC8 0
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#define RDIMM_RC9 0
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#define RDIMM_RC10 0x2
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#define RDIMM_RC11 0x0
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#if defined(MIXED_DIMM_STATIC) || !defined(CONFIG_SPD_EEPROM)
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#define DUNIT_STATIC
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#endif
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#if defined(MIXED_DIMM_STATIC) || defined(CONFIG_SPD_EEPROM)
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/*
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* This flag allows the user to change the dram refresh cycle in ps,
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* only in case of SPD or MIX DIMM topology
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*/
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#define TREFI_USER_EN
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#ifdef TREFI_USER_EN
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#define TREFI_USER 3900000
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#endif
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#endif
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#ifdef CONFIG_SPD_EEPROM
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/*
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* AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards.
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* Enables I2C auto detection different options
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*/
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#if defined(CONFIG_DB_88F78X60) || defined(CONFIG_DB_88F78X60_REV2) || \
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defined(CONFIG_DB_784MP_GP)
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#define AUTO_DETECTION_SUPPORT
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#endif
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#endif
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#endif /* __DDR3_AXP_CONFIG_H */
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