142 lines
3.9 KiB
C
142 lines
3.9 KiB
C
/*
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* Mentor USB OTG Core functionality common for both Host and Device
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* functionality.
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*
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* Copyright (c) 2008 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
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*/
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#include <common.h>
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#include "musb_core.h"
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struct musb_regs *musbr;
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/*
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* program the mentor core to start (enable interrupts, dma, etc.)
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*/
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void musb_start(void)
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{
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u8 devctl;
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/* disable all interrupts */
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writew(0, &musbr->intrtxe);
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writew(0, &musbr->intrrxe);
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writeb(0, &musbr->intrusbe);
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writeb(0, &musbr->testmode);
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/* put into basic highspeed mode and start session */
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writeb(MUSB_POWER_HSENAB, &musbr->power);
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#if defined(CONFIG_MUSB_HCD)
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devctl = readb(&musbr->devctl);
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writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl);
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#endif
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}
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/*
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* This function configures the endpoint configuration. The musb hcd or musb
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* device implementation can use this function to configure the endpoints
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* and set the FIFO sizes. Note: The summation of FIFO sizes of all endpoints
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* should not be more than the available FIFO size.
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*
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* epinfo - Pointer to EP configuration table
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* cnt - Number of entries in the EP conf table.
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*/
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void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt)
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{
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u16 csr;
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u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */
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u32 fifosize;
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u8 idx;
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while (cnt--) {
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/* prepare fifosize to write to register */
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fifosize = epinfo->epsize >> 3;
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idx = ffs(fifosize) - 1;
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writeb(epinfo->epnum, &musbr->index);
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if (epinfo->epdir) {
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/* Configure fifo size and fifo base address */
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writeb(idx, &musbr->txfifosz);
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writew(fifoaddr >> 3, &musbr->txfifoadd);
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#if defined(CONFIG_MUSB_HCD)
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/* clear the data toggle bit */
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csr = readw(&musbr->txcsr);
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writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
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#endif
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/* Flush fifo if required */
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if (csr & MUSB_TXCSR_TXPKTRDY)
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writew(csr | MUSB_TXCSR_FLUSHFIFO,
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&musbr->txcsr);
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} else {
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/* Configure fifo size and fifo base address */
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writeb(idx, &musbr->rxfifosz);
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writew(fifoaddr >> 3, &musbr->rxfifoadd);
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#if defined(CONFIG_MUSB_HCD)
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/* clear the data toggle bit */
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csr = readw(&musbr->rxcsr);
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writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
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#endif
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/* Flush fifo if required */
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if (csr & MUSB_RXCSR_RXPKTRDY)
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writew(csr | MUSB_RXCSR_FLUSHFIFO,
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&musbr->rxcsr);
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}
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fifoaddr += epinfo->epsize;
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epinfo++;
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}
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}
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/*
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* This function writes data to endpoint fifo
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*
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* ep - endpoint number
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* length - number of bytes to write to FIFO
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* fifo_data - Pointer to data buffer that contains the data to write
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*/
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void write_fifo(u8 ep, u32 length, void *fifo_data)
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{
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u8 *data = (u8 *)fifo_data;
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/* select the endpoint index */
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writeb(ep, &musbr->index);
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/* write the data to the fifo */
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while (length--)
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writeb(*data++, &musbr->fifox[ep]);
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}
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/*
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* This function reads data from endpoint fifo
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*
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* ep - endpoint number
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* length - number of bytes to read from FIFO
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* fifo_data - pointer to data buffer into which data is read
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*/
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void read_fifo(u8 ep, u32 length, void *fifo_data)
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{
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u8 *data = (u8 *)fifo_data;
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/* select the endpoint index */
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writeb(ep, &musbr->index);
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/* read the data to the fifo */
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while (length--)
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*data++ = readb(&musbr->fifox[ep]);
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}
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