348 lines
8.9 KiB
ArmAsm
348 lines
8.9 KiB
ArmAsm
/*
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* Copyright (C) 2013,2014 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/psci.h>
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.pushsection ._secure.text, "ax"
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.arch_extension sec
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.align 5
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.globl _psci_vectors
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_psci_vectors:
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b default_psci_vector @ reset
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b default_psci_vector @ undef
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b _smc_psci @ smc
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b default_psci_vector @ pabort
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b default_psci_vector @ dabort
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b default_psci_vector @ hyp
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b default_psci_vector @ irq
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b psci_fiq_enter @ fiq
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ENTRY(psci_fiq_enter)
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movs pc, lr
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ENDPROC(psci_fiq_enter)
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.weak psci_fiq_enter
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ENTRY(default_psci_vector)
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movs pc, lr
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ENDPROC(default_psci_vector)
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.weak default_psci_vector
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ENTRY(psci_version)
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ENTRY(psci_cpu_suspend)
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ENTRY(psci_cpu_off)
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ENTRY(psci_cpu_on)
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ENTRY(psci_affinity_info)
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ENTRY(psci_migrate)
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ENTRY(psci_migrate_info_type)
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ENTRY(psci_migrate_info_up_cpu)
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ENTRY(psci_system_off)
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ENTRY(psci_system_reset)
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ENTRY(psci_features)
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ENTRY(psci_cpu_freeze)
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ENTRY(psci_cpu_default_suspend)
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ENTRY(psci_node_hw_state)
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ENTRY(psci_system_suspend)
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ENTRY(psci_set_suspend_mode)
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ENTRY(psi_stat_residency)
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ENTRY(psci_stat_count)
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mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
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mov pc, lr
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ENDPROC(psci_stat_count)
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ENDPROC(psi_stat_residency)
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ENDPROC(psci_set_suspend_mode)
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ENDPROC(psci_system_suspend)
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ENDPROC(psci_node_hw_state)
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ENDPROC(psci_cpu_default_suspend)
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ENDPROC(psci_cpu_freeze)
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ENDPROC(psci_features)
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ENDPROC(psci_system_reset)
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ENDPROC(psci_system_off)
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ENDPROC(psci_migrate_info_up_cpu)
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ENDPROC(psci_migrate_info_type)
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ENDPROC(psci_migrate)
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ENDPROC(psci_affinity_info)
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ENDPROC(psci_cpu_on)
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ENDPROC(psci_cpu_off)
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ENDPROC(psci_cpu_suspend)
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ENDPROC(psci_version)
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.weak psci_version
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.weak psci_cpu_suspend
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.weak psci_cpu_off
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.weak psci_cpu_on
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.weak psci_affinity_info
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.weak psci_migrate
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.weak psci_migrate_info_type
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.weak psci_migrate_info_up_cpu
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.weak psci_system_off
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.weak psci_system_reset
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.weak psci_features
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.weak psci_cpu_freeze
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.weak psci_cpu_default_suspend
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.weak psci_node_hw_state
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.weak psci_system_suspend
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.weak psci_set_suspend_mode
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.weak psi_stat_residency
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.weak psci_stat_count
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_psci_table:
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.word ARM_PSCI_FN_CPU_SUSPEND
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.word psci_cpu_suspend
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.word ARM_PSCI_FN_CPU_OFF
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.word psci_cpu_off
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.word ARM_PSCI_FN_CPU_ON
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.word psci_cpu_on
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.word ARM_PSCI_FN_MIGRATE
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.word psci_migrate
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.word ARM_PSCI_0_2_FN_PSCI_VERSION
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.word psci_version
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.word ARM_PSCI_0_2_FN_CPU_SUSPEND
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.word psci_cpu_suspend
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.word ARM_PSCI_0_2_FN_CPU_OFF
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.word psci_cpu_off
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.word ARM_PSCI_0_2_FN_CPU_ON
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.word psci_cpu_on
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.word ARM_PSCI_0_2_FN_AFFINITY_INFO
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.word psci_affinity_info
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.word ARM_PSCI_0_2_FN_MIGRATE
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.word psci_migrate
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.word ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE
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.word psci_migrate_info_type
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.word ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU
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.word psci_migrate_info_up_cpu
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.word ARM_PSCI_0_2_FN_SYSTEM_OFF
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.word psci_system_off
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.word ARM_PSCI_0_2_FN_SYSTEM_RESET
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.word psci_system_reset
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.word ARM_PSCI_1_0_FN_PSCI_FEATURES
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.word psci_features
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.word ARM_PSCI_1_0_FN_CPU_FREEZE
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.word psci_cpu_freeze
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.word ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
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.word psci_cpu_default_suspend
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.word ARM_PSCI_1_0_FN_NODE_HW_STATE
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.word psci_node_hw_state
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.word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
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.word psci_system_suspend
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.word ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
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.word psci_set_suspend_mode
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.word ARM_PSCI_1_0_FN_STAT_RESIDENCY
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.word psi_stat_residency
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.word ARM_PSCI_1_0_FN_STAT_COUNT
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.word psci_stat_count
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.word 0
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.word 0
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_smc_psci:
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push {r4-r7,lr}
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@ Switch to secure
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mrc p15, 0, r7, c1, c1, 0
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bic r4, r7, #1
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mcr p15, 0, r4, c1, c1, 0
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isb
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adr r4, _psci_table
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1: ldr r5, [r4] @ Load PSCI function ID
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ldr r6, [r4, #4] @ Load target PC
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cmp r5, #0 @ If reach the end, bail out
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moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid)
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beq 2f
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cmp r0, r5 @ If not matching, try next entry
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addne r4, r4, #8
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bne 1b
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blx r6 @ Execute PSCI function
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@ Switch back to non-secure
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2: mcr p15, 0, r7, c1, c1, 0
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pop {r4-r7, lr}
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movs pc, lr @ Return to the kernel
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@ Requires dense and single-cluster CPU ID space
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ENTRY(psci_get_cpu_id)
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mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */
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and r0, r0, #0xff /* return CPU ID in cluster */
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bx lr
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ENDPROC(psci_get_cpu_id)
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.weak psci_get_cpu_id
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/* Imported from Linux kernel */
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ENTRY(psci_v7_flush_dcache_all)
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stmfd sp!, {r4-r5, r7, r9-r11, lr}
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished @ if loc is 0, then no need to clean
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mov r10, #0 @ start clean at cache level 0
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flush_levels:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mrs r9, cpsr @ make cssr&csidr read atomic
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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msr cpsr_c, r9
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop1:
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mov r9, r7 @ create working copy of max index
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loop2:
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orr r11, r10, r4, lsl r5 @ factor way and cache number into r11
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orr r11, r11, r9, lsl r2 @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the index
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bge loop2
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subs r4, r4, #1 @ decrement the way
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bge loop1
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt flush_levels
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finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb st
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isb
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ldmfd sp!, {r4-r5, r7, r9-r11, lr}
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bx lr
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ENDPROC(psci_v7_flush_dcache_all)
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ENTRY(psci_disable_smp)
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mrc p15, 0, r0, c1, c0, 1 @ ACTLR
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bic r0, r0, #(1 << 6) @ Clear SMP bit
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mcr p15, 0, r0, c1, c0, 1 @ ACTLR
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isb
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dsb
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bx lr
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ENDPROC(psci_disable_smp)
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.weak psci_disable_smp
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ENTRY(psci_enable_smp)
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mrc p15, 0, r0, c1, c0, 1 @ ACTLR
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orr r0, r0, #(1 << 6) @ Set SMP bit
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mcr p15, 0, r0, c1, c0, 1 @ ACTLR
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isb
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bx lr
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ENDPROC(psci_enable_smp)
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.weak psci_enable_smp
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ENTRY(psci_cpu_off_common)
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push {lr}
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bl psci_v7_flush_dcache_all
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clrex @ Why???
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR
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bic r0, r0, #(1 << 2) @ Clear C bit
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mcr p15, 0, r0, c1, c0, 0 @ SCTLR
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isb
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dsb
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bl psci_v7_flush_dcache_all
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clrex @ Why???
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bl psci_disable_smp
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pop {lr}
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bx lr
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ENDPROC(psci_cpu_off_common)
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@ The stacks are allocated in reverse order, i.e.
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@ the stack for CPU0 has the highest memory address.
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@
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@ -------------------- __secure_stack_end
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@ | CPU0 target PC |
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@ |------------------|
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@ | |
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@ | CPU0 stack |
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@ | |
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@ |------------------| __secure_stack_end - 1KB
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@ | . |
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@ | . |
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@ | . |
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@ | . |
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@ -------------------- __secure_stack_start
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@
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@ This expects CPU ID in r0 and returns stack top in r0
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LENTRY(psci_get_cpu_stack_top)
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@ stack top = __secure_stack_end - (cpuid << ARM_PSCI_STACK_SHIFT)
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ldr r3, =__secure_stack_end
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sub r0, r3, r0, LSL #ARM_PSCI_STACK_SHIFT
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sub r0, r0, #4 @ Save space for target PC
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bx lr
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ENDPROC(psci_get_cpu_stack_top)
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@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in
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@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across
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@ this function.
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ENTRY(psci_stack_setup)
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mov r6, lr
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mov r7, r0
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bl psci_get_cpu_id @ CPU ID => r0
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bl psci_get_cpu_stack_top @ stack top => r0
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mov sp, r0
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mov r0, r7
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bx r6
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ENDPROC(psci_stack_setup)
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ENTRY(psci_arch_init)
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mov pc, lr
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ENDPROC(psci_arch_init)
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.weak psci_arch_init
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ENTRY(psci_arch_cpu_entry)
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mov pc, lr
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ENDPROC(psci_arch_cpu_entry)
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.weak psci_arch_cpu_entry
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ENTRY(psci_cpu_entry)
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bl psci_enable_smp
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bl _nonsec_init
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bl psci_stack_setup
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bl psci_arch_cpu_entry
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bl psci_get_cpu_id @ CPU ID => r0
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mov r2, r0 @ CPU ID => r2
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bl psci_get_context_id @ context id => r0
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mov r1, r0 @ context id => r1
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mov r0, r2 @ CPU ID => r0
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bl psci_get_target_pc @ target PC => r0
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b _do_nonsec_entry
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ENDPROC(psci_cpu_entry)
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.popsection
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