59 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			59 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			C
		
	
	
	
| /* SPDX-License-Identifier: GPL-2.0+ */
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| /*
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|  * Copyright (C) 2013 Boundary Devices Inc.
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|  */
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| #ifndef __ASM_ARCH_MX6DLS_DDR_H__
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| #define __ASM_ARCH_MX6DLS_DDR_H__
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| 
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| #ifndef CONFIG_MX6DL
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| #ifndef CONFIG_MX6S
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| #error "wrong CPU"
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| #endif
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| #endif
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| 
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| #define MX6_IOM_DRAM_DQM0	0x020e0470
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| #define MX6_IOM_DRAM_DQM1	0x020e0474
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| #define MX6_IOM_DRAM_DQM2	0x020e0478
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| #define MX6_IOM_DRAM_DQM3	0x020e047c
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| #define MX6_IOM_DRAM_DQM4	0x020e0480
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| #define MX6_IOM_DRAM_DQM5	0x020e0484
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| #define MX6_IOM_DRAM_DQM6	0x020e0488
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| #define MX6_IOM_DRAM_DQM7	0x020e048c
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| 
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| #define MX6_IOM_DRAM_CAS	0x020e0464
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| #define MX6_IOM_DRAM_RAS	0x020e0490
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| #define MX6_IOM_DRAM_RESET	0x020e0494
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| #define MX6_IOM_DRAM_SDCLK_0	0x020e04ac
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| #define MX6_IOM_DRAM_SDCLK_1	0x020e04b0
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| #define MX6_IOM_DRAM_SDBA2	0x020e04a0
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| #define MX6_IOM_DRAM_SDCKE0	0x020e04a4
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| #define MX6_IOM_DRAM_SDCKE1	0x020e04a8
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| #define MX6_IOM_DRAM_SDODT0	0x020e04b4
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| #define MX6_IOM_DRAM_SDODT1	0x020e04b8
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| 
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| #define MX6_IOM_DRAM_SDQS0	0x020e04bc
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| #define MX6_IOM_DRAM_SDQS1	0x020e04c0
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| #define MX6_IOM_DRAM_SDQS2	0x020e04c4
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| #define MX6_IOM_DRAM_SDQS3	0x020e04c8
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| #define MX6_IOM_DRAM_SDQS4	0x020e04cc
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| #define MX6_IOM_DRAM_SDQS5	0x020e04d0
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| #define MX6_IOM_DRAM_SDQS6	0x020e04d4
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| #define MX6_IOM_DRAM_SDQS7	0x020e04d8
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| 
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| #define MX6_IOM_GRP_B0DS	0x020e0764
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| #define MX6_IOM_GRP_B1DS	0x020e0770
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| #define MX6_IOM_GRP_B2DS	0x020e0778
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| #define MX6_IOM_GRP_B3DS	0x020e077c
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| #define MX6_IOM_GRP_B4DS	0x020e0780
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| #define MX6_IOM_GRP_B5DS	0x020e0784
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| #define MX6_IOM_GRP_B6DS	0x020e078c
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| #define MX6_IOM_GRP_B7DS	0x020e0748
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| #define MX6_IOM_GRP_ADDDS	0x020e074c
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| #define MX6_IOM_DDRMODE_CTL	0x020e0750
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| #define MX6_IOM_GRP_DDRPKE	0x020e0754
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| #define MX6_IOM_GRP_DDRMODE	0x020e0760
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| #define MX6_IOM_GRP_CTLDS	0x020e076c
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| #define MX6_IOM_GRP_DDR_TYPE	0x020e0774
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| 
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| #endif	/*__ASM_ARCH_MX6S_DDR_H__ */
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