36 lines
782 B
C
36 lines
782 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2016 Rockchip Electronics Co.,Ltd
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*/
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#ifndef _ASM_ARCH_SYS_PROTO_H
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#define _ASM_ARCH_SYS_PROTO_H
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#ifdef CONFIG_ROCKCHIP_RK3288
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#include <asm/armv7.h>
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static void configure_l2ctlr(void)
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{
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uint32_t l2ctlr;
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l2ctlr = read_l2ctlr();
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l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
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/*
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* Data RAM write latency: 2 cycles
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* Data RAM read latency: 2 cycles
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* Data RAM setup latency: 1 cycle
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* Tag RAM write latency: 1 cycle
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* Tag RAM read latency: 1 cycle
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* Tag RAM setup latency: 1 cycle
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*/
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l2ctlr |= (1 << 3 | 1 << 0);
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write_l2ctlr(l2ctlr);
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}
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#endif /* CONFIG_ROCKCHIP_RK3288 */
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/* provided to defeat compiler optimisation in board_init_f() */
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void gru_dummy_function(int i);
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#endif /* _ASM_ARCH_SYS_PROTO_H */
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