603 lines
15 KiB
C
603 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3128.h>
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#include <asm/arch/hardware.h>
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#include <bitfield.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/rk3128-cru.h>
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#include <linux/log2.h>
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enum {
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VCO_MAX_HZ = 2400U * 1000000,
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VCO_MIN_HZ = 600 * 1000000,
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OUTPUT_MAX_HZ = 2400U * 1000000,
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OUTPUT_MIN_HZ = 24 * 1000000,
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};
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
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.refdiv = _refdiv,\
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
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/* use integer mode*/
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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{
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int pll_id = rk_pll_id(clk_id);
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struct rk3128_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions. */
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uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
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uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
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debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n",
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pll, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_hz, output_hz);
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
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/* use integer mode */
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rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
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/* Power down */
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rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
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rk_clrsetreg(&pll->con0,
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PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
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(div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
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rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
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(div->postdiv2 << PLL_POSTDIV2_SHIFT |
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div->refdiv << PLL_REFDIV_SHIFT));
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/* Power Up */
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rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
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/* waiting for pll lock */
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while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
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udelay(1);
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return 0;
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}
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static int pll_para_config(u32 freq_hz, struct pll_div *div)
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{
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u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0;
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u32 postdiv1, postdiv2 = 1;
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u32 fref_khz;
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u32 diff_khz, best_diff_khz;
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const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
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const u32 max_postdiv1 = 7, max_postdiv2 = 7;
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u32 vco_khz;
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u32 freq_khz = freq_hz / 1000;
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if (!freq_hz) {
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printf("%s: the frequency can't be 0 Hz\n", __func__);
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return -1;
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}
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postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz);
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if (postdiv1 > max_postdiv1) {
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postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
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postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
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}
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vco_khz = freq_khz * postdiv1 * postdiv2;
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if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) ||
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postdiv2 > max_postdiv2) {
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printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n",
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__func__, freq_hz);
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return -1;
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}
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div->postdiv1 = postdiv1;
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div->postdiv2 = postdiv2;
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best_diff_khz = vco_khz;
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for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
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fref_khz = ref_khz / refdiv;
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fbdiv = vco_khz / fref_khz;
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if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
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continue;
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diff_khz = vco_khz - fbdiv * fref_khz;
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if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
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fbdiv++;
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diff_khz = fref_khz - diff_khz;
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}
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if (diff_khz >= best_diff_khz)
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continue;
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best_diff_khz = diff_khz;
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div->refdiv = refdiv;
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div->fbdiv = fbdiv;
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}
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if (best_diff_khz > 4 * (1000)) {
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printf("%s: Failed to match output frequency %u bestis %u Hz\n",
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__func__, freq_hz,
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best_diff_khz * 1000);
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return -1;
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}
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return 0;
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}
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static void rkclk_init(struct rk3128_cru *cru)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK | APLL_MODE_MASK,
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GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
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APLL_MODE_SLOW << APLL_MODE_SHIFT);
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/* init pll */
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rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
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rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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/*
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* select apll as cpu/core clock pll source and
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* set up dependent divisors for PERI and ACLK clocks.
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* core hz : apll = 1:1
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*/
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aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
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assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
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pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
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assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
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CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
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0 << CORE_DIV_CON_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
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aclk_div << CORE_ACLK_DIV_SHIFT |
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pclk_div << CORE_PERI_DIV_SHIFT);
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/*
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* select gpll as pd_bus bus clock source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
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assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
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pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
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assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
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hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
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assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
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BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
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aclk_div << BUS_ACLK_DIV_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
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pclk_div << BUS_PCLK_DIV_SHIFT |
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hclk_div << BUS_HCLK_DIV_SHIFT);
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/*
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* select gpll as pd_peri bus clock source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
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assert((1 << hclk_div) * PERI_HCLK_HZ ==
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PERI_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
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assert((1 << pclk_div) * PERI_PCLK_HZ ==
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PERI_ACLK_HZ && pclk_div < 0x8);
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rk_clrsetreg(&cru->cru_clksel_con[10],
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PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
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PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
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PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
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pclk_div << PERI_PCLK_DIV_SHIFT |
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hclk_div << PERI_HCLK_DIV_SHIFT |
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aclk_div << PERI_ACLK_DIV_SHIFT);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK | APLL_MODE_MASK | CPLL_MODE_MASK,
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GPLL_MODE_NORM << GPLL_MODE_SHIFT |
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APLL_MODE_NORM << APLL_MODE_SHIFT |
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CPLL_MODE_NORM << CPLL_MODE_SHIFT);
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/*fix NAND controller working clock max to 150Mhz */
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rk_clrsetreg(&cru->cru_clksel_con[2],
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NANDC_PLL_SEL_MASK | NANDC_CLK_DIV_MASK,
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NANDC_PLL_SEL_GPLL << NANDC_PLL_SEL_SHIFT |
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3 << NANDC_CLK_DIV_SHIFT);
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}
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/* Get pll rate by id */
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static u32 rkclk_pll_get_rate(struct rk3128_cru *cru,
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enum rk_clk_id clk_id)
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{
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u32 refdiv, fbdiv, postdiv1, postdiv2;
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u32 con;
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int pll_id = rk_pll_id(clk_id);
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struct rk3128_pll *pll = &cru->pll[pll_id];
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static u8 clk_shift[CLK_COUNT] = {
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0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
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GPLL_MODE_SHIFT, 0xff
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};
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static u32 clk_mask[CLK_COUNT] = {
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0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
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GPLL_MODE_MASK, 0xff
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};
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uint shift;
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uint mask;
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con = readl(&cru->cru_mode_con);
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shift = clk_shift[clk_id];
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mask = clk_mask[clk_id];
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switch ((con & mask) >> shift) {
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case GPLL_MODE_SLOW:
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return OSC_HZ;
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case GPLL_MODE_NORM:
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/* normal mode */
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con = readl(&pll->con0);
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postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
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fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
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con = readl(&pll->con1);
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postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
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refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
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return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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case GPLL_MODE_DEEP:
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default:
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return 32768;
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}
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}
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static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate,
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int periph)
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{
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uint src_rate;
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uint div, mux;
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u32 con;
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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case SCLK_EMMC_SAMPLE:
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con = readl(&cru->cru_clksel_con[12]);
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mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
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div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
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break;
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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con = readl(&cru->cru_clksel_con[11]);
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mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
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div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
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break;
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default:
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return -EINVAL;
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}
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src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
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return DIV_TO_RATE(src_rate, div);
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}
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static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate,
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int periph, uint freq)
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{
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int src_clk_div;
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int mux;
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debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
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/* mmc clock defaulg div 2 internal, need provide double in cru */
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src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
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if (src_clk_div > 128) {
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src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
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mux = EMMC_SEL_24M;
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} else {
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mux = EMMC_SEL_GPLL;
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}
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switch (periph) {
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case HCLK_EMMC:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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EMMC_PLL_MASK | EMMC_DIV_MASK,
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mux << EMMC_PLL_SHIFT |
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(src_clk_div - 1) << EMMC_DIV_SHIFT);
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break;
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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rk_clrsetreg(&cru->cru_clksel_con[11],
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MMC0_PLL_MASK | MMC0_DIV_MASK,
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mux << MMC0_PLL_SHIFT |
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(src_clk_div - 1) << MMC0_DIV_SHIFT);
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break;
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default:
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return -EINVAL;
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}
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return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
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}
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static ulong rk3128_peri_get_pclk(struct rk3128_cru *cru, ulong clk_id)
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{
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u32 div, con;
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switch (clk_id) {
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case PCLK_I2C0:
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case PCLK_I2C1:
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case PCLK_I2C2:
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case PCLK_I2C3:
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case PCLK_PWM:
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con = readl(&cru->cru_clksel_con[10]);
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div = con >> 12 & 0x3;
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break;
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default:
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printf("do not support this peripheral bus\n");
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return -EINVAL;
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}
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return DIV_TO_RATE(PERI_ACLK_HZ, div);
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}
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static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz)
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{
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int src_clk_div;
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src_clk_div = PERI_ACLK_HZ / hz;
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assert(src_clk_div - 1 < 4);
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switch (clk_id) {
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case PCLK_I2C0:
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case PCLK_I2C1:
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case PCLK_I2C2:
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case PCLK_I2C3:
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case PCLK_PWM:
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rk_setreg(&cru->cru_clksel_con[10],
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((src_clk_div - 1) << 12));
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break;
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default:
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printf("do not support this peripheral bus\n");
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return -EINVAL;
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}
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return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div);
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}
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static ulong rk3128_saradc_get_clk(struct rk3128_cru *cru)
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{
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u32 div, val;
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val = readl(&cru->cru_clksel_con[24]);
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div = bitfield_extract(val, SARADC_DIV_CON_SHIFT,
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SARADC_DIV_CON_WIDTH);
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return DIV_TO_RATE(OSC_HZ, div);
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}
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static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
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assert(src_clk_div < 128);
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rk_clrsetreg(&cru->cru_clksel_con[24],
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SARADC_DIV_CON_MASK,
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src_clk_div << SARADC_DIV_CON_SHIFT);
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return rk3128_saradc_get_clk(cru);
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}
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static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz)
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{
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int src_clk_div;
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struct pll_div cpll_config = {0};
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src_clk_div = GPLL_HZ / hz;
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assert(src_clk_div - 1 < 31);
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switch (clk_id) {
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case ACLK_VIO0:
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rk_clrsetreg(&cru->cru_clksel_con[31],
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VIO0_PLL_MASK | VIO0_DIV_MASK,
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VIO0_SEL_GPLL << VIO0_PLL_SHIFT |
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(src_clk_div - 1) << VIO0_DIV_SHIFT);
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break;
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case ACLK_VIO1:
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rk_clrsetreg(&cru->cru_clksel_con[31],
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VIO1_PLL_MASK | VIO1_DIV_MASK,
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VIO1_SEL_GPLL << VIO1_PLL_SHIFT |
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(src_clk_div - 1) << VIO1_DIV_SHIFT);
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break;
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case DCLK_LCDC:
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if (pll_para_config(hz, &cpll_config))
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return -1;
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rkclk_set_pll(cru, CLK_CODEC, &cpll_config);
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rk_clrsetreg(&cru->cru_clksel_con[27],
|
|
DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_CON_MASK,
|
|
DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_SEL_SHIFT |
|
|
(1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
|
|
break;
|
|
default:
|
|
printf("do not support this vop freq\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return hz;
|
|
}
|
|
|
|
static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id)
|
|
{
|
|
u32 div, con, parent;
|
|
|
|
switch (clk_id) {
|
|
case ACLK_VIO0:
|
|
con = readl(&cru->cru_clksel_con[31]);
|
|
div = con & 0x1f;
|
|
parent = GPLL_HZ;
|
|
break;
|
|
case ACLK_VIO1:
|
|
con = readl(&cru->cru_clksel_con[31]);
|
|
div = (con >> 8) & 0x1f;
|
|
parent = GPLL_HZ;
|
|
break;
|
|
case DCLK_LCDC:
|
|
con = readl(&cru->cru_clksel_con[27]);
|
|
div = (con >> 8) & 0xfff;
|
|
parent = rkclk_pll_get_rate(cru, CLK_CODEC);
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
return DIV_TO_RATE(parent, div);
|
|
}
|
|
|
|
static ulong rk3128_clk_get_rate(struct clk *clk)
|
|
{
|
|
struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
|
|
|
|
switch (clk->id) {
|
|
case 0 ... 63:
|
|
return rkclk_pll_get_rate(priv->cru, clk->id);
|
|
case PCLK_I2C0:
|
|
case PCLK_I2C1:
|
|
case PCLK_I2C2:
|
|
case PCLK_I2C3:
|
|
case PCLK_PWM:
|
|
return rk3128_peri_get_pclk(priv->cru, clk->id);
|
|
case SCLK_SARADC:
|
|
return rk3128_saradc_get_clk(priv->cru);
|
|
case DCLK_LCDC:
|
|
case ACLK_VIO0:
|
|
case ACLK_VIO1:
|
|
return rk3128_vop_get_rate(priv->cru, clk->id);
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
}
|
|
|
|
static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
|
|
ulong new_rate, gclk_rate;
|
|
|
|
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
|
|
switch (clk->id) {
|
|
case 0 ... 63:
|
|
return 0;
|
|
case DCLK_LCDC:
|
|
case ACLK_VIO0:
|
|
case ACLK_VIO1:
|
|
new_rate = rk3128_vop_set_clk(priv->cru,
|
|
clk->id, rate);
|
|
break;
|
|
case HCLK_EMMC:
|
|
new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
|
|
clk->id, rate);
|
|
break;
|
|
case PCLK_I2C0:
|
|
case PCLK_I2C1:
|
|
case PCLK_I2C2:
|
|
case PCLK_I2C3:
|
|
case PCLK_PWM:
|
|
new_rate = rk3128_peri_set_pclk(priv->cru, clk->id, rate);
|
|
break;
|
|
case SCLK_SARADC:
|
|
new_rate = rk3128_saradc_set_clk(priv->cru, rate);
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return new_rate;
|
|
}
|
|
|
|
static struct clk_ops rk3128_clk_ops = {
|
|
.get_rate = rk3128_clk_get_rate,
|
|
.set_rate = rk3128_clk_set_rate,
|
|
};
|
|
|
|
static int rk3128_clk_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct rk3128_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->cru = dev_read_addr_ptr(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk3128_clk_probe(struct udevice *dev)
|
|
{
|
|
struct rk3128_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
rkclk_init(priv->cru);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk3128_clk_bind(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
struct udevice *sys_child;
|
|
struct sysreset_reg *priv;
|
|
|
|
/* The reset driver does not have a device node, so bind it here */
|
|
ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
|
|
&sys_child);
|
|
if (ret) {
|
|
debug("Warning: No sysreset driver: ret=%d\n", ret);
|
|
} else {
|
|
priv = malloc(sizeof(struct sysreset_reg));
|
|
priv->glb_srst_fst_value = offsetof(struct rk3128_cru,
|
|
cru_glb_srst_fst_value);
|
|
priv->glb_srst_snd_value = offsetof(struct rk3128_cru,
|
|
cru_glb_srst_snd_value);
|
|
sys_child->priv = priv;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id rk3128_clk_ids[] = {
|
|
{ .compatible = "rockchip,rk3128-cru" },
|
|
{ .compatible = "rockchip,rk3126-cru" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(rockchip_rk3128_cru) = {
|
|
.name = "clk_rk3128",
|
|
.id = UCLASS_CLK,
|
|
.of_match = rk3128_clk_ids,
|
|
.priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
|
|
.ofdata_to_platdata = rk3128_clk_ofdata_to_platdata,
|
|
.ops = &rk3128_clk_ops,
|
|
.bind = rk3128_clk_bind,
|
|
.probe = rk3128_clk_probe,
|
|
};
|