47 lines
1.7 KiB
C
47 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#ifndef _UTIL_CSR_H_
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#define _UTIL_CSR_H_
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#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
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#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
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#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
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#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
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#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
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#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
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#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
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#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
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#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
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#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
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#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108)
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#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114)
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#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118)
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#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200)
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#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204)
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#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208)
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#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c)
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#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210)
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#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214)
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#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218)
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#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c)
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#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220)
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#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224)
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#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228)
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#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c)
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#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230)
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#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234)
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#define UTIL_AXI_CTRL (UTIL_CSR_BASE_ADDR + 0x240)
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#endif /* _UTIL_CSR_H_ */
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