1148 lines
26 KiB
C
1148 lines
26 KiB
C
/*
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* board.c
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*
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* Board functions for Netmodule nmhw21 board, based on AM335x EVB
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*
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* Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <serial.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clk_synthesizer.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <spi.h>
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#include <pca953x.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <environment.h>
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#include <watchdog.h>
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#include <libfdt.h>
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#include <miiphy.h>
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#include "../common/bdparser.h"
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#include "../common/board_descriptor.h"
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#include "board.h"
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#include "da9063.h"
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#include "sja1105.h"
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#include "ui.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* CPU GPIOs
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*
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* (J18) GPIO0_16: ETH_SW_RST~ (V2.0)
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* (K15) GPIO0_17: CTRL.INT~
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* (T10) GPIO0_23: CAN_TERM1~ (V1.0)
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* (T17) GPIO0_30: LED0.RD
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*
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* (T12) GPIO1_12: SIM_SW
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* (V13) GPIO1_14: GNSS_RST~
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* (U13) GPIO1_15: CAN_TERM0~ (V1.0)
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* (R14) GPIO1_20: BT_EN
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* (V15) GPIO1_21: GSM_PWR_EN
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* (U15) GPIO1_22: LED1.RD
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* (V16) GPIO1_24: LED1.GN
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* (U16) GPIO1_25: RST_GSM
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* (T16) GPIO1_26: WLAN_EN
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* (V17) GPIO1_27: WLAN_IRQ
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* (U18) GPIO1_28: LED0.GN
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*
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* (U3) GPIO2_16: SIM_PRES~ (V2.0)
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* (R6) GPIO2_25: RST_ETH~
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*
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* (J17) GPIO3_4: GNSS_EXTINT
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* (K18) GPIO3_9: CTRL.W_DIS
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* (L18) GPIO3_10: CTRL.RST
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* (C12) GPIO3_17: UI_RST~
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* (A14) GPIO3_21: RST_HUB~ (USB)
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*/
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#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
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#define GPIO_LED0_RED GPIO_TO_PIN(0, 30)
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#define GPIO_LED0_GREEN GPIO_TO_PIN(1, 28)
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#define GPIO_LED1_RED GPIO_TO_PIN(1, 22)
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#define GPIO_LED1_GREEN GPIO_TO_PIN(1, 24)
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#define GPIO_RST_GSM GPIO_TO_PIN(1, 25)
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#define GPIO_PWR_GSM GPIO_TO_PIN(1, 21)
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#define GPIO_WLAN_EN GPIO_TO_PIN(1, 26)
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#define GPIO_BT_EN GPIO_TO_PIN(1, 20)
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#define GPIO_RST_GNSS GPIO_TO_PIN(1, 14)
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#define GPIO_RST_ETH_SW_N GPIO_TO_PIN(0, 16)
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#define GPIO_RST_ETH_N GPIO_TO_PIN(2, 25)
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#define GPIO_RST_USB_HUB_N GPIO_TO_PIN(3, 21)
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#define GPIO_RST_UM_N GPIO_TO_PIN(3, 10)
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#define GPIO_CTRL_WDIS_N GPIO_TO_PIN(3, 9)
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#define GPIO_CTRL_INT_N GPIO_TO_PIN(0, 17)
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#define GPIO_RST_UI_N GPIO_TO_PIN(3, 17)
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#define CAN0_TERM_N GPIO_TO_PIN(1, 15)
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#define CAN1_TERM_N GPIO_TO_PIN(0, 23)
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#define GPIO_SIM_SEL GPIO_TO_PIN(1, 12)
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#define GPIO_SIM_PRES_N GPIO_TO_PIN(2, 16)
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/*
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* PMIC GPIOs
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*
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* GPIO_5: EN_SUPPLY_GSM
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* GPIO_8: VOLTAGE_SEL_UM
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* GPIO_9: EN_SUPPLY_UM
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*/
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#define PMIC_GSM_SUPPLY_EN_IO 5
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#define PMIC_UM_SUPPLY_VSEL_IO 8
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#define PMIC_UM_SUPPLY_EN_IO 9
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/*
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* I2C IO Extender (On UI Interface)
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*/
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#define IOEXT_LED1_RED_MASK (1U << 7)
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#define IOEXT_LED1_GREEN_MASK (1U << 6)
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#define IOEXT_LED2_RED_MASK (1U << 8)
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#define IOEXT_LED2_GREEN_MASK (1U << 9)
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#define IOEXT_LEDS_ALL_MASK (0x03C0)
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#define DDR3_CLOCK_FREQUENCY (400)
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#if !defined(CONFIG_SPL_BUILD)
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/* Hardware version information of mainboard, loaded by get_hw_version() */
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static int hw_ver = -1;
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static int hw_rev = -1;
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static int hw_patch = -1;
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#endif
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#if !defined(CONFIG_SPL_BUILD)
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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#endif
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#define I2C_BD_EEPROM_BUS (1)
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#define BD_EEPROM_ADDR (0x50) /* CPU BD EEPROM (8kByte) is at 50 (A0) */
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#define BD_ADDRESS (0x0000) /* Board descriptor at beginning of EEPROM */
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#define PD_ADDRESS (0x0200) /* Product descriptor */
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#define PARTITION_ADDRESS (0x0600) /* Partition Table */
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static BD_Context bdctx[3]; /* The descriptor contexts */
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#define CONFIG_OF_BOARD_SETUP
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#if !defined(CONFIG_SPL_BUILD)
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/* SPI1 for Ethernet switch configuration */
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static struct module_pin_mux spi1_pin_mux[] = {
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{OFFSET(ecap0_in_pwm0_out), (MODE(4) | PULLUDEN | PULLDOWN_EN | RXACTIVE)}, /* (C18) spi1_clk */
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{OFFSET(uart0_rtsn), (MODE(4) | PULLUDEN | PULLUP_EN)}, /* (E17) spi1_mosi */
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{OFFSET(uart0_ctsn), (MODE(4) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (E18) spi1_miso */
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{OFFSET(uart0_txd), (MODE(1) | PULLUDEN | PULLUP_EN)}, /* (E16) spi1_cs1 */
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{-1}
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#if 0
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{OFFSET(uart0_rxd), (MODE(1) | PULLUDEN | PULLUP_EN)}, /* (E15) spi1_cs0 */
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#endif
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};
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#endif
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static void request_and_set_gpio(int gpio, const char *name, int value)
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{
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int ret;
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ret = gpio_request(gpio, name);
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if (ret < 0) {
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printf("%s: Unable to request %s\n", __func__, name);
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return;
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}
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ret = gpio_direction_output(gpio, value);
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if (ret < 0) {
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printf("%s: Unable to set %s as output\n", __func__, name);
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goto err_free_gpio;
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}
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return;
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err_free_gpio:
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gpio_free(gpio);
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}
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#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
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#define REQUEST_AND_CLEAR_GPIO(N) request_and_set_gpio(N, #N, 0);
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static void init_leds(void)
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{
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REQUEST_AND_SET_GPIO(GPIO_LED0_RED);
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REQUEST_AND_SET_GPIO(GPIO_LED0_GREEN);
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REQUEST_AND_SET_GPIO(GPIO_LED1_RED);
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REQUEST_AND_SET_GPIO(GPIO_LED1_GREEN);
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}
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static void set_status_led(int red, int green)
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{
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gpio_set_value(GPIO_LED0_RED, red);
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gpio_set_value(GPIO_LED0_GREEN, green);
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}
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static void set_indicator_led(int red, int green)
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{
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gpio_set_value(GPIO_LED1_RED, red);
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gpio_set_value(GPIO_LED1_GREEN, green);
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}
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static void init_i2c(void)
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{
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i2c_set_bus_num(0);
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_set_bus_num(1);
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_set_bus_num(0);
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}
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static int _bd_init(void)
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{
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int old_bus;
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old_bus = i2c_get_bus_num();
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i2c_set_bus_num(I2C_BD_EEPROM_BUS);
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if (bd_get_context(&bdctx[0], BD_EEPROM_ADDR, BD_ADDRESS) != 0) {
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printf("%s() no valid bd found\n", __func__);
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return -1;
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}
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if (bd_get_context(&bdctx[1], BD_EEPROM_ADDR, PD_ADDRESS) != 0) {
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printf("%s() no valid pd found (legacy support)\n", __func__);
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return -1;
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}
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if (bd_get_context(&bdctx[2], BD_EEPROM_ADDR, PARTITION_ADDRESS) != 0) {
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printf("%s() no valid partition table found\n", __func__);
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return -1;
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}
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bd_register_context_list(bdctx, ARRAY_SIZE(bdctx));
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i2c_set_bus_num(old_bus);
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return 0;
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}
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static bool is_jtag_boot(uint32_t address)
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{
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char* jtag_token = (char*)address;
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if (strcmp(jtag_token, "JTAGBOOT") == 0) {
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strcpy(jtag_token, "jtagboot");
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return true;
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}
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else {
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return false;
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}
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}
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/*
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* Read header information from EEPROM into global structure.
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*/
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static inline int __maybe_unused read_eeprom(void)
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{
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return _bd_init();
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}
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/*
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* Selects console for SPL.
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* U-Boot console is defined by CONFIG_CONS_INDEX (via menuconfig)
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*/
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struct serial_device *default_serial_console(void)
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{
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enable_uart2_pin_mux();
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/* Provide UART on UART2 regardless of boot mode */
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return &eserial3_device;
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/* TODO: Shall we keep this? */
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#if 0
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if (spl_boot_device() == BOOT_DEVICE_UART) {
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/* SPL Boot -> UART0 (later used for SPI) */
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enable_uart0_pin_mux();
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return &eserial1_device;
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}
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else {
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/* eMMC Boot --> UART2 */
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enable_uart2_pin_mux();
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return &eserial3_device;
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}
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#endif
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}
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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static const struct ddr_data ddr3_data = {
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/* Ratios were optimized by DDR3 training software from TI */
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/* TODO: Evaluate new values and update */
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.datardsratio0 = 0x39, /* 0x39 */
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.datawdsratio0 = 0x3f, /* 0x40 */
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.datafwsratio0 = 0x98, /* 0x96 */
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.datawrsratio0 = 0x7d, /* 0x7d */
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = 0x61A, /* 32ms > 85°C */
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.sdram_tim1 = 0x0AAAE51B,
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.sdram_tim2 = 0x246B7FDA,
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.sdram_tim3 = 0x50FFE67F,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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#define OSC (V_OSCK/1000000)
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struct dpll_params dpll_ddr = {
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DDR3_CLOCK_FREQUENCY, OSC-1, 1, -1, -1, -1, -1
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};
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static void init_pmic_spl(void)
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{
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int rc;
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int bus;
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uint8_t val;
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/* PMIC basic configuration */
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da9063_init(CONFIG_PMIC_I2C_BUS);
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bus = da9063_claim_i2c_bus();
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/* Workaround for pre v1.3 config (reports ID 0x3e -> 3.14) */
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rc = da9063_get_reg(PMIC_REG_CONFIG_ID, &val);
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if (!rc && (val == 0x3E)) {
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printf("Detected pre v1.3 PMIC config. Fixing registers\n");
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/* Include +3V3_SENSORS (LDO3) in sequencing and enable manually */
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(void)da9063_set_reg(PMIC_REG_ID_4_3, 0x07 /* Slot 7 */);
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(void)da9063_set_reg(PMIC_REG_LDO3_CONT, PMIC_LDOx_EN_MASK);
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/*
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* Set AUTO Bit for sequencer controlled supplies, so that they get
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* enabled when leaving power down state
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*/
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(void)da9063_set_reg(PMIC_REG_CONFIG_E, 0x3B);
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(void)da9063_set_reg(PMIC_REG_CONFIG_G, 0x44);
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/*
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* Clear sequencer target state bit (xxx_CONT::xxx_CONF bit), so that
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* regulators are disabled when entering power down state.
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*/
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(void)da9063_set_reg(PMIC_REG_LDO3_CONT, PMIC_LDOx_EN_MASK);
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(void)da9063_set_reg(PMIC_REG_LDO7_CONT, PMIC_LDOx_EN_MASK);
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(void)da9063_set_reg(PMIC_REG_BCORE1_CONT, PMIC_LDOx_EN_MASK);
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(void)da9063_set_reg(PMIC_REG_BCORE2_CONT, PMIC_LDOx_EN_MASK);
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(void)da9063_set_reg(PMIC_REG_BPERI_CONT, PMIC_LDOx_EN_MASK);
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(void)da9063_set_reg(PMIC_REG_BIO_CONT, PMIC_LDOx_EN_MASK);
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(void)da9063_set_reg(PMIC_REG_BMEM_CONT, PMIC_LDOx_EN_MASK);
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}
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/* Enable +3V3_GNSS (LDO6) */
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(void)da9063_set_reg(PMIC_REG_LDO6_CONT, PMIC_LDOx_EN_MASK);
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mdelay(2);
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/* Enable +5V_CAN (LDO11 Switch) */
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(void)da9063_set_reg(PMIC_REG_LDO11_CONT, PMIC_LDOx_EN_MASK);
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mdelay(2);
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da9063_release_i2c_bus(bus);
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}
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void am33xx_spl_board_init(void)
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{
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/* Set CPU speed to 600 MHz (fix) */
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dpll_mpu_opp100.m = MPUPLL_M_600;
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/* Set CORE Frequencies to OPP100 (600MHz) */
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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/* Configure I2C busses */
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init_i2c();
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/* Setup PMIC */
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init_pmic_spl();
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init_leds();
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set_status_led(1, 1); /* Orange */
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/* Set MPU Frequency to what we detected now that voltages are set */
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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/* Debugger can place marker at end of SRAM to stop boot here */
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if (is_jtag_boot(CONFIG_JTAG_MARKER_SPL))
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{
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puts("Detected JTAG boot, executing bkpt #0\n");
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__asm__ __volatile__ ("bkpt #0");
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}
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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dpll_ddr.n = (get_osclk() / 1000000) - 1;
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return &dpll_ddr;
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}
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void set_uart_mux_conf(void)
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{
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/* TODO: Set depending on boot mode (SPL/UBoot, eMMC/UART) */
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enable_uart0_pin_mux();
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enable_uart2_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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const struct ctrl_ioregs ioregs = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE
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};
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void sdram_init(void)
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{
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config_ddr(DDR3_CLOCK_FREQUENCY, &ioregs,
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&ddr3_data,
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&ddr3_cmd_ctrl_data,
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&ddr3_emif_reg_data, 0);
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}
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#if !defined(CONFIG_SPL_BUILD)
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static void init_ethernet(void)
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{
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REQUEST_AND_CLEAR_GPIO(GPIO_RST_ETH_N);
|
|
/* Minimum Reset Pulse = 5us (switch), 20us (TJA1100), 100us (SMSC8720) */
|
|
mdelay(1);
|
|
gpio_set_value(GPIO_RST_ETH_N, 1);
|
|
}
|
|
|
|
static void init_ethernet_v2(void)
|
|
{
|
|
/* Put switch and PHYs in reset */
|
|
REQUEST_AND_CLEAR_GPIO(GPIO_RST_ETH_N);
|
|
REQUEST_AND_CLEAR_GPIO(GPIO_RST_ETH_SW_N);
|
|
|
|
/* Take switch out of reset. Minimum Reset Pulse = 5us */
|
|
mdelay(1);
|
|
gpio_set_value(GPIO_RST_ETH_SW_N, 1);
|
|
}
|
|
|
|
static void init_ethernet_phys_v2(void)
|
|
{
|
|
/* Take Ethernet PHYs out of reset */
|
|
/* Minimum Reset Pulse = 20us (TJA1102), 100us (SMSC8720) */
|
|
mdelay(1);
|
|
gpio_set_value(GPIO_RST_ETH_N, 1);
|
|
}
|
|
|
|
static void configure_ethernet_switch(void)
|
|
{
|
|
static struct spi_slave *spi = 0;
|
|
|
|
if (spi == 0) {
|
|
configure_module_pin_mux(spi1_pin_mux);
|
|
spi_init();
|
|
|
|
/* Maximum bitrate supported by switch is 17.8 MHz */
|
|
spi = spi_setup_slave(CONFIG_SJA1105_SPI_BUS,
|
|
CONFIG_SJA1105_SPI_CS,
|
|
15000000 /* Frequency 15 MHz */,
|
|
SPI_MODE_1);
|
|
|
|
sja1105_init(spi);
|
|
}
|
|
|
|
spi_claim_bus(spi);
|
|
|
|
/* 1ms delay after init before first SPI acces */
|
|
mdelay(1);
|
|
|
|
sja1105_configure_firmware();
|
|
|
|
/* Configure clocks */
|
|
sja1105_configure_mode_and_clocks();
|
|
|
|
/* Configure IO pads */
|
|
sja1105_configure_io();
|
|
|
|
spi_release_bus(spi);
|
|
}
|
|
|
|
static void configure_broadr_phys(void)
|
|
{
|
|
unsigned char phy;
|
|
const char *devname;
|
|
int err = 0;
|
|
|
|
/* Get current device */
|
|
devname = miiphy_get_current_dev();
|
|
/* configure BroadR PHY TJA1100 as slave and restart FSM*/
|
|
for (phy = 6; phy <= 7 && err == 0; phy++) {
|
|
/* Extended control register : bit 15 ->link control disabled */
|
|
if (0 != miiphy_write (devname, phy, 0x11, 0x0004)) { err++; }
|
|
/* Configuration register 1 : bit 15 -> PHY configured as Slave */
|
|
if (0 != miiphy_write (devname, phy, 0x12, 0x0910)) { err++; }
|
|
/* Extended control register : link control enable and training restart */
|
|
if (0 != miiphy_write (devname, phy, 0x11, 0x9A04)) { err++; }
|
|
}
|
|
if (err != 0) {
|
|
puts("BroadR not ready, ");
|
|
}
|
|
else {
|
|
puts("BroadR ready, ");
|
|
}
|
|
}
|
|
|
|
static void init_usb_hub(void)
|
|
{
|
|
REQUEST_AND_CLEAR_GPIO(GPIO_RST_USB_HUB_N);
|
|
/* Minimum Reset Pulse = 1us */
|
|
mdelay(2);
|
|
gpio_set_value(GPIO_RST_USB_HUB_N, 1);
|
|
}
|
|
|
|
static void init_user_module(void)
|
|
{
|
|
int bus;
|
|
|
|
bus = da9063_claim_i2c_bus();
|
|
|
|
/* TODO: Open Drain as UM can drive against mainboard */
|
|
/* TODO: Check whether reset shall be driven by mainboard at all */
|
|
/* REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_RST_PHY_N); */
|
|
/* OMAP3 does not feature open drain pins, thus configure pin as input */
|
|
/* gpio_direction_input(NETBIRD_GPIO_RST_PHY_N); */
|
|
|
|
puts("UM: ");
|
|
|
|
REQUEST_AND_CLEAR_GPIO(GPIO_RST_UM_N); /* Assert reset (active low) */
|
|
REQUEST_AND_CLEAR_GPIO(GPIO_CTRL_WDIS_N) /* TODO: CHECK */
|
|
|
|
da9063_set_gpio(PMIC_UM_SUPPLY_EN_IO, 0); /* Switch Supply off */
|
|
mdelay(30); /* Give time to discharge output */
|
|
|
|
da9063_set_gpio(PMIC_UM_SUPPLY_VSEL_IO, 0); /* Set voltage to 3.3V */
|
|
mdelay(1);
|
|
|
|
da9063_set_gpio(PMIC_UM_SUPPLY_EN_IO, 1); /* Enable Supply */
|
|
mdelay(10);
|
|
|
|
gpio_direction_input(GPIO_RST_UM_N); /* Release reset (open drain) */
|
|
|
|
puts("ready\n");
|
|
|
|
da9063_release_i2c_bus(bus);
|
|
}
|
|
|
|
static void init_sim_mux(void)
|
|
{
|
|
/*
|
|
* Switch onboard SIM to onboard modem (Mux = 1)
|
|
*/
|
|
REQUEST_AND_SET_GPIO(GPIO_SIM_SEL);
|
|
|
|
/*
|
|
* Inform modem that SIM is installed
|
|
* - uBlox TOBY-L2 Datasheet UBX-13004573 - R24
|
|
* - uBlox TOBY-L2-MPCI-L2_SysIntegrManual_(UBX-13004618) - R26
|
|
* 1.8.2 SIM detection interface
|
|
*/
|
|
REQUEST_AND_CLEAR_GPIO(GPIO_SIM_PRES_N);
|
|
}
|
|
|
|
static void init_gsm(void)
|
|
{
|
|
int bus;
|
|
|
|
/*
|
|
* Perform power up sequence for TOBY-L2 modem.
|
|
*
|
|
* Modem is initially disabled and does not start automatically.
|
|
* Enable power and start modem by "pressing" POWER_ON_OFF input for 1.0s.
|
|
*
|
|
* References:
|
|
* - uBlox TOBY-L2 Datasheet UBX-13004573 - R24
|
|
* 2.3.1 Module power-on
|
|
*/
|
|
|
|
bus = da9063_claim_i2c_bus();
|
|
|
|
puts("GSM: ");
|
|
|
|
/* TODO: Keep Power-On and use GSM Modem Reset Signal to restart */
|
|
|
|
REQUEST_AND_SET_GPIO(GPIO_RST_GSM); /* Assert reset (active high) */
|
|
REQUEST_AND_CLEAR_GPIO(GPIO_PWR_GSM); /* Keep power switch inactive (released) */
|
|
|
|
da9063_set_gpio(PMIC_GSM_SUPPLY_EN_IO, 0); /* Switch GSM Supply off */
|
|
mdelay(30+100); /* Give time to discharge supply */
|
|
/* Keep of for 100ms, #3.3.2 */
|
|
|
|
da9063_set_gpio(PMIC_GSM_SUPPLY_EN_IO, 1); /* Enable GSM supply */
|
|
mdelay(10);
|
|
|
|
gpio_set_value(GPIO_RST_GSM, 0); /* Take modem out of reset */
|
|
|
|
puts("ready\n");
|
|
|
|
da9063_release_i2c_bus(bus);
|
|
}
|
|
|
|
static void init_gnss(void)
|
|
{
|
|
/*
|
|
* Release GNSS reset line, so that modem starts up early
|
|
*/
|
|
REQUEST_AND_SET_GPIO(GPIO_RST_GNSS);
|
|
}
|
|
|
|
#endif /* !defined(CONFIG_SPL_BUILD) */
|
|
|
|
|
|
/*
|
|
* Basic board specific setup. Pinmux has been handled already.
|
|
* Not called in SPL build.
|
|
*/
|
|
int board_init(void)
|
|
{
|
|
#if defined(CONFIG_HW_WATCHDOG)
|
|
hw_watchdog_init();
|
|
#endif
|
|
|
|
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
|
|
|
/* Configure I2C busses */
|
|
init_i2c();
|
|
|
|
da9063_init(CONFIG_PMIC_I2C_BUS);
|
|
|
|
/* UI detection */
|
|
REQUEST_AND_SET_GPIO(GPIO_RST_UI_N);
|
|
ui_init(CONFIG_UI_I2C_BUS);
|
|
|
|
/* Let user know we're starting */
|
|
init_leds();
|
|
set_status_led(1, 1); /* Orange */
|
|
set_indicator_led(0, 0); /* Off */
|
|
ui_set_top_led(1, 1);
|
|
ui_set_bottom_led(0, 0);
|
|
|
|
printf("OSC: %lu MHz\n", get_osclk()/1000000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if !defined(CONFIG_SPL_BUILD)
|
|
|
|
void set_console(void)
|
|
{
|
|
const char *defaultconsole = getenv("defaultconsole");
|
|
|
|
if (defaultconsole == 0) {
|
|
/* Use the default console */
|
|
setenv("defaultconsole", "ttyS2");
|
|
}
|
|
}
|
|
|
|
#if 0 // remove legacy NRSW stuff ...
|
|
static void set_devicetree_name(void)
|
|
{
|
|
char devicetreename[64];
|
|
|
|
/* add hardware versions to environment */
|
|
if (bd_get_devicetree(devicetreename, sizeof(devicetreename)) != 0) {
|
|
printf("Devicetree name not found, using default name\n");
|
|
strcpy(devicetreename, "am335x-nmhw21-prod1.dtb");
|
|
}
|
|
|
|
setenv("fdt_image", devicetreename);
|
|
}
|
|
|
|
static void set_root_partition(void)
|
|
{
|
|
int boot_partition;
|
|
|
|
/* add active root partition to environment */
|
|
boot_partition = bd_get_boot_partition();
|
|
if (boot_partition > 1) {
|
|
boot_partition = 0;
|
|
}
|
|
|
|
/* mmcblk0p1 => root0, mmcblk0p2 => root1 so +1 */
|
|
setenv_ulong("root_part", boot_partition + 1);
|
|
}
|
|
#endif
|
|
|
|
static void get_hw_version(void)
|
|
{
|
|
char hw_versions[16];
|
|
char new_env[256]; /* current bootargs = 84 bytes */
|
|
|
|
bd_get_hw_version(&hw_ver, &hw_rev);
|
|
bd_get_hw_patch(&hw_patch);
|
|
printf("MB: V%d.%d\n", hw_ver, hw_rev);
|
|
|
|
/* add hardware versions to environment */
|
|
/* TODO: Remove ! */
|
|
snprintf(hw_versions, sizeof(hw_versions), "CP=%d.%d", hw_ver, hw_rev);
|
|
snprintf(new_env, sizeof(new_env), "setenv bootargs $bootargs %s", hw_versions);
|
|
setenv("add_version_bootargs", new_env);
|
|
}
|
|
|
|
static void get_pmic_version(void)
|
|
{
|
|
uint8_t val = 0x00;
|
|
uint8_t ver, rev;
|
|
int bus;
|
|
int rc;
|
|
|
|
bus = da9063_claim_i2c_bus();
|
|
|
|
rc = da9063_get_reg(PMIC_REG_CONFIG_ID, &val);
|
|
if (!rc) {
|
|
ver = (val >> 4) & 0xF;
|
|
rev = (val >> 0) & 0xF;
|
|
} else {
|
|
ver = 0;
|
|
rev = 0;
|
|
}
|
|
|
|
da9063_release_i2c_bus(bus);
|
|
|
|
/* Quirk:
|
|
* If reported version is 3.14, this is one of the 5 prototypes which have
|
|
* been programmed multiple times --> Treat these as 1.0
|
|
*/
|
|
if ((ver == 3) && (rev == 14)) {
|
|
ver = 1;
|
|
rev = 0;
|
|
}
|
|
|
|
printf("PMIC: V%d.%d\n", ver, rev);
|
|
}
|
|
|
|
|
|
static void check_jtag_boot(void)
|
|
{
|
|
if (is_jtag_boot(CONFIG_JTAG_MARKER_UBOOT)) {
|
|
setenv ("bootcmd", "");
|
|
puts("Detected JTAG boot. Waiting on command line\n");
|
|
}
|
|
}
|
|
|
|
#if 0
|
|
|
|
static void check_fct(void)
|
|
{
|
|
/* Check whether an I2C device (EEPROM) is present at address 0xA2/0x51
|
|
* In this case we are connected to the factory test station.
|
|
* Clear the bootcmd, so that test system can easily connect.
|
|
*/
|
|
|
|
int old_bus;
|
|
|
|
old_bus = i2c_get_bus_num();
|
|
i2c_set_bus_num(I2C_BD_EEPROM_BUS);
|
|
|
|
/* If probe fails we are sure no eeprom is connected */
|
|
if (i2c_probe(0x51) == 0) {
|
|
printf("Entering fct mode\n");
|
|
setenv ("bootcmd", "");
|
|
}
|
|
|
|
i2c_set_bus_num(old_bus);
|
|
}
|
|
|
|
|
|
static bool get_button_state(void)
|
|
{
|
|
u8 state = 0x00;
|
|
|
|
/* TODO: Claim Bus */
|
|
(void)da9063_get_reg(PMIC_REG_STATUS_A, &state);
|
|
|
|
return (state & 0x01) == 0x01;
|
|
}
|
|
|
|
static void blink_led(void)
|
|
{
|
|
const int pulse_width = 400*1000; /* 400ms */
|
|
|
|
/* Assumes green status LED is on */
|
|
udelay(pulse_width);
|
|
set_status_led(0, 0);
|
|
udelay(pulse_width);
|
|
set_status_led(0, 1);
|
|
}
|
|
|
|
static void check_reset_button(void)
|
|
{
|
|
int counter = 0;
|
|
|
|
/* Check how long button is pressed */
|
|
do {
|
|
if (!get_button_state())
|
|
break;
|
|
|
|
udelay(100*1000); /* 100ms */
|
|
counter += 100;
|
|
|
|
if (counter == 2000) {
|
|
/* Indicate factory reset threshold */
|
|
blink_led();
|
|
}
|
|
else if (counter == 12000) {
|
|
/* Indicate recovery boot threshold */
|
|
blink_led();
|
|
blink_led();
|
|
}
|
|
} while (counter < 12000);
|
|
|
|
if (counter < 2000) {
|
|
/* Don't do anything for duration < 2s */
|
|
}
|
|
else if (counter < 12000)
|
|
{
|
|
/* Do factory reset for duration between 2s and 12s */
|
|
char new_bootargs[512];
|
|
char *bootargs = getenv("bootargs");
|
|
|
|
if (bootargs == 0) bootargs="";
|
|
|
|
printf("Do factory reset during boot...\n");
|
|
|
|
strncpy(new_bootargs, bootargs, sizeof(new_bootargs));
|
|
strncat(new_bootargs, " factory-reset", sizeof(new_bootargs));
|
|
|
|
setenv("bootargs", new_bootargs);
|
|
}
|
|
else
|
|
{
|
|
/* Boot into recovery for duration > 12s */
|
|
|
|
printf("Booting recovery image...\n");
|
|
|
|
/* Set bootcmd to run recovery */
|
|
setenv("bootcmd", "run recovery");
|
|
|
|
/* set consoledev to external port */
|
|
/* setenv("consoledev", "ttyS1"); */
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#endif /* !defined(CONFIG_SPL_BUILD) */
|
|
|
|
|
|
int board_late_init(void)
|
|
{
|
|
#if !defined(CONFIG_SPL_BUILD)
|
|
int ui_ver = -1;
|
|
|
|
if (read_eeprom() < 0) {
|
|
puts("Could not get board ID.\n");
|
|
}
|
|
|
|
get_hw_version();
|
|
get_pmic_version();
|
|
// set_root_partition();
|
|
// set_devicetree_name();
|
|
|
|
/* Initialize pins */
|
|
REQUEST_AND_CLEAR_GPIO(GPIO_WLAN_EN);
|
|
REQUEST_AND_CLEAR_GPIO(GPIO_BT_EN);
|
|
|
|
REQUEST_AND_SET_GPIO(CAN0_TERM_N); /* Unused on V2.0 */
|
|
REQUEST_AND_SET_GPIO(CAN1_TERM_N);
|
|
|
|
ui_ver = ui_version();
|
|
switch (ui_ver) {
|
|
case 1: puts("UI: V1.0\n"); break;
|
|
case 2: puts("UI: V2.0\n"); break;
|
|
default: puts("UI: N/A\n"); break;
|
|
}
|
|
|
|
/* FIXME: Problem switch reset lines of switch and PHY
|
|
* Clocks for PHY are only present once switch is configured
|
|
* Thus need to repeat reset sequence once in order to have
|
|
* PHY also properly bootstrapped.
|
|
* Should be reworked by giving switch a dedicated reset line
|
|
*/
|
|
if (hw_ver == 1) {
|
|
init_ethernet();
|
|
configure_ethernet_switch();
|
|
/* FIXME: Reset ETH system again to pin strap PHY */
|
|
mdelay(10);
|
|
gpio_set_value(GPIO_RST_ETH_N, 0);
|
|
mdelay(10);
|
|
gpio_set_value(GPIO_RST_ETH_N, 1);
|
|
configure_ethernet_switch();
|
|
}
|
|
else {
|
|
/* TODO: Verify operation */
|
|
init_ethernet_v2();
|
|
configure_ethernet_switch();
|
|
|
|
/* Now that Ethernet switch is working, PHY clocks are present.
|
|
* Take PHYs out of reset.
|
|
*/
|
|
init_ethernet_phys_v2();
|
|
}
|
|
|
|
init_usb_hub();
|
|
init_user_module();
|
|
init_sim_mux();
|
|
init_gsm();
|
|
init_gnss();
|
|
|
|
/*
|
|
check_reset_button();
|
|
*/
|
|
|
|
set_status_led(0, 1); /* Green */
|
|
ui_set_top_led(0, 1);
|
|
|
|
|
|
/*
|
|
check_fct();
|
|
*/
|
|
check_jtag_boot();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
#ifndef CONFIG_DM_ETH
|
|
|
|
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
|
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
|
static void cpsw_control(int enabled)
|
|
{
|
|
/* VTP can be added here */
|
|
|
|
return;
|
|
}
|
|
|
|
static struct cpsw_slave_data cpsw_slaves[] = {
|
|
{
|
|
.slave_reg_ofs = 0x208,
|
|
.sliver_reg_ofs = 0xd80,
|
|
.phy_if = PHY_INTERFACE_MODE_RMII,
|
|
.phy_addr = 1
|
|
}
|
|
};
|
|
|
|
static struct cpsw_platform_data cpsw_data = {
|
|
.mdio_base = CPSW_MDIO_BASE,
|
|
.cpsw_base = CPSW_BASE,
|
|
.mdio_div = 0xff,
|
|
.channels = 8,
|
|
.cpdma_reg_ofs = 0x800,
|
|
.slaves = 1,
|
|
.slave_data = cpsw_slaves,
|
|
.ale_reg_ofs = 0xd00,
|
|
.ale_entries = 1024,
|
|
.host_port_reg_ofs = 0x108,
|
|
.hw_stats_reg_ofs = 0x900,
|
|
.bd_ram_ofs = 0x2000,
|
|
.mac_control = (1 << 5),
|
|
.control = cpsw_control,
|
|
.host_port_num = 0,
|
|
.version = CPSW_CTRL_VERSION_2,
|
|
};
|
|
#endif
|
|
|
|
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
|
|
defined(CONFIG_SPL_BUILD)) || \
|
|
((defined(CONFIG_DRIVER_TI_CPSW) || \
|
|
defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
|
|
!defined(CONFIG_SPL_BUILD))
|
|
|
|
static void set_mac_address(int index, uchar mac[6])
|
|
{
|
|
/* Then take mac from bd */
|
|
if (is_valid_ethaddr(mac)) {
|
|
eth_setenv_enetaddr_by_index("eth", index, mac);
|
|
}
|
|
else {
|
|
printf("Trying to set invalid MAC address");
|
|
}
|
|
}
|
|
|
|
/* TODO: Update doc */
|
|
/*
|
|
* This function will:
|
|
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
|
|
* in the environment
|
|
* Perform fixups to the PHY present on certain boards. We only need this
|
|
* function in:
|
|
* - SPL with either CPSW or USB ethernet support
|
|
* - Full U-Boot, with either CPSW or USB ethernet
|
|
* Build in only these cases to avoid warnings about unused variables
|
|
* when we build an SPL that has neither option but full U-Boot will.
|
|
*/
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
int n = 0;
|
|
__maybe_unused uint8_t mac_addr0[6] = {02,00,00,00,00,01};
|
|
#if !defined(CONFIG_SPL_BUILD)
|
|
#ifdef CONFIG_DRIVER_TI_CPSW
|
|
cpsw_data.mdio_div = 0x3E;
|
|
|
|
bd_get_mac(0, mac_addr0, sizeof(mac_addr0));
|
|
set_mac_address(0, mac_addr0);
|
|
|
|
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
|
|
|
|
{
|
|
int rv = cpsw_register(&cpsw_data);
|
|
if (rv < 0)
|
|
{
|
|
printf("Error %d registering CPSW switch\n", rv);
|
|
} else {
|
|
n += rv;
|
|
}
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_USB_ETHER) && \
|
|
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
|
|
if (is_valid_ethaddr(mac_addr0)) {
|
|
eth_setenv_enetaddr("usbnet_devaddr", mac_addr0);
|
|
}
|
|
|
|
{
|
|
int rv = usb_eth_initialize(bis);
|
|
if (rv < 0)
|
|
{
|
|
printf("Error %d registering USB_ETHER\n", rv);
|
|
} else {
|
|
n += rv;
|
|
}
|
|
}
|
|
#endif
|
|
/* Enable BroadR PHYs, set to slave mode */
|
|
configure_broadr_phys();
|
|
return n;
|
|
}
|
|
#endif
|
|
|
|
#endif /* CONFIG_DM_ETH */
|
|
|
|
#ifdef CONFIG_SPL_LOAD_FIT
|
|
int board_fit_config_name_match(const char *name)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_SPL_BUILD)
|
|
|
|
static void ft_hw_version(void *blob)
|
|
{
|
|
int node_offset;
|
|
char hw_version[16];
|
|
|
|
snprintf(hw_version, sizeof(hw_version), "%d.%d.%d", hw_ver, hw_rev, hw_patch);
|
|
|
|
node_offset = fdt_path_offset(blob, "/");
|
|
if (node_offset != -1) {
|
|
fdt_setprop_string(blob, node_offset, "nm,carrierboard,version", hw_version);
|
|
}
|
|
}
|
|
|
|
static void ft_led(void *blob)
|
|
{
|
|
int ui_hw_version = ui_version();
|
|
|
|
if (ui_hw_version > 0) {
|
|
int node_offset;
|
|
|
|
/* TODO: UI LEDs are different from V1 to V2 */
|
|
node_offset = fdt_path_offset(blob, "/leds/led@4/");
|
|
if (node_offset != -1) {
|
|
fdt_setprop_string(blob, node_offset, "status", "okay");
|
|
}
|
|
node_offset = fdt_path_offset(blob, "/leds/led@5/");
|
|
if (node_offset != -1) {
|
|
fdt_setprop_string(blob, node_offset, "status", "okay");
|
|
}
|
|
node_offset = fdt_path_offset(blob, "/leds/led@6/");
|
|
if (node_offset != -1) {
|
|
fdt_setprop_string(blob, node_offset, "status", "okay");
|
|
}
|
|
node_offset = fdt_path_offset(blob, "/leds/led@7/");
|
|
if (node_offset != -1) {
|
|
fdt_setprop_string(blob, node_offset, "status", "okay");
|
|
}
|
|
}
|
|
}
|
|
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
ft_hw_version(blob);
|
|
ft_led(blob);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif
|