693 lines
13 KiB
ArmAsm
693 lines
13 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Low-level board setup code for TI DaVinci SoC based boards.
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Partially based on TI sources, original copyrights follow:
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*/
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/*
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* Board specific setup info
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
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*
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* Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
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*
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* Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
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*
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* Modified for DV-EVM board by Swaminathan S, Nov 2005
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*/
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#include <config.h>
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#define MDSTAT_STATE 0x3f
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.globl lowlevel_init
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lowlevel_init:
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#ifdef CONFIG_SOC_DM644X
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/*-------------------------------------------------------*
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* Mask all IRQs by setting all bits in the EINT default *
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*-------------------------------------------------------*/
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mov r1, $0
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ldr r0, =EINT_ENABLE0
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str r1, [r0]
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ldr r0, =EINT_ENABLE1
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str r1, [r0]
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/*------------------------------------------------------*
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* Put the GEM in reset *
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*------------------------------------------------------*/
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/* Put the GEM in reset */
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ldr r8, PSC_GEM_FLAG_CLEAR
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ldr r6, MDCTL_GEM
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ldr r7, [r6]
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and r7, r7, r8
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str r7, [r6]
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/* Enable the Power Domain Transition Command */
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ldr r6, PTCMD
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ldr r7, [r6]
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orr r7, r7, $0x02
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str r7, [r6]
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/* Check for Transition Complete(PTSTAT) */
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checkStatClkStopGem:
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ldr r6, PTSTAT
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ldr r7, [r6]
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ands r7, r7, $0x02
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bne checkStatClkStopGem
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/* Check for GEM Reset Completion */
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checkGemStatClkStop:
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ldr r6, MDSTAT_GEM
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ldr r7, [r6]
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ands r7, r7, $0x100
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bne checkGemStatClkStop
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/* Do this for enabling a WDT initiated reset this is a workaround
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for a chip bug. Not required under normal situations */
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ldr r6, P1394
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mov r10, $0
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str r10, [r6]
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/*------------------------------------------------------*
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* Enable L1 & L2 Memories in Fast mode *
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*------------------------------------------------------*/
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ldr r6, DFT_ENABLE
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mov r10, $0x01
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str r10, [r6]
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ldr r6, MMARG_BRF0
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ldr r10, MMARG_BRF0_VAL
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str r10, [r6]
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ldr r6, DFT_ENABLE
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mov r10, $0
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str r10, [r6]
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/*------------------------------------------------------*
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* DDR2 PLL Initialization *
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*------------------------------------------------------*/
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/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
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mov r10, $0
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ldr r6, PLL2_CTL
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ldr r7, PLL_CLKSRC_MASK
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ldr r8, [r6]
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and r8, r8, r7
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mov r9, r10, lsl $8
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orr r8, r8, r9
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str r8, [r6]
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/* Select the PLLEN source */
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ldr r7, PLL_ENSRC_MASK
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and r8, r8, r7
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str r8, [r6]
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/* Bypass the PLL */
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ldr r7, PLL_BYPASS_MASK
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and r8, r8, r7
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str r8, [r6]
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/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
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mov r10, $0x20
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WaitPPL2Loop:
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subs r10, r10, $1
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bne WaitPPL2Loop
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/* Reset the PLL */
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ldr r7, PLL_RESET_MASK
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and r8, r8, r7
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str r8, [r6]
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/* Power up the PLL */
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ldr r7, PLL_PWRUP_MASK
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and r8, r8, r7
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str r8, [r6]
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/* Enable the PLL from Disable Mode */
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ldr r7, PLL_DISABLE_ENABLE_MASK
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and r8, r8, r7
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str r8, [r6]
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/* Program the PLL Multiplier */
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ldr r6, PLL2_PLLM
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mov r2, $0x17 /* 162 MHz */
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str r2, [r6]
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/* Program the PLL2 Divisor Value */
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ldr r6, PLL2_DIV2
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mov r3, $0x01
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str r3, [r6]
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/* Program the PLL2 Divisor Value */
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ldr r6, PLL2_DIV1
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mov r4, $0x0b /* 54 MHz */
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str r4, [r6]
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/* PLL2 DIV2 MMR */
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ldr r8, PLL2_DIV_MASK
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ldr r6, PLL2_DIV2
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ldr r9, [r6]
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and r8, r8, r9
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mov r9, $0x01
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mov r9, r9, lsl $15
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orr r8, r8, r9
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str r8, [r6]
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/* Program the GOSET bit to take new divider values */
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ldr r6, PLL2_PLLCMD
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ldr r7, [r6]
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orr r7, r7, $0x01
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str r7, [r6]
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/* Wait for Done */
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ldr r6, PLL2_PLLSTAT
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doneLoop_0:
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ldr r7, [r6]
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ands r7, r7, $0x01
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bne doneLoop_0
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/* PLL2 DIV1 MMR */
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ldr r8, PLL2_DIV_MASK
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ldr r6, PLL2_DIV1
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ldr r9, [r6]
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and r8, r8, r9
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mov r9, $0x01
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mov r9, r9, lsl $15
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orr r8, r8, r9
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str r8, [r6]
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/* Program the GOSET bit to take new divider values */
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ldr r6, PLL2_PLLCMD
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ldr r7, [r6]
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orr r7, r7, $0x01
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str r7, [r6]
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/* Wait for Done */
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ldr r6, PLL2_PLLSTAT
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doneLoop:
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ldr r7, [r6]
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ands r7, r7, $0x01
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bne doneLoop
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/* Wait for PLL to Reset Properly */
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mov r10, $0x218
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ResetPPL2Loop:
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subs r10, r10, $1
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bne ResetPPL2Loop
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/* Bring PLL out of Reset */
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ldr r6, PLL2_CTL
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ldr r8, [r6]
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orr r8, r8, $0x08
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str r8, [r6]
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/* Wait for PLL to Lock */
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ldr r10, PLL_LOCK_COUNT
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PLL2Lock:
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subs r10, r10, $1
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bne PLL2Lock
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/* Enable the PLL */
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ldr r6, PLL2_CTL
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ldr r8, [r6]
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orr r8, r8, $0x01
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str r8, [r6]
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/*------------------------------------------------------*
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* Issue Soft Reset to DDR Module *
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*------------------------------------------------------*/
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/* Shut down the DDR2 LPSC Module */
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ldr r8, PSC_FLAG_CLEAR
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ldr r6, MDCTL_DDR2
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ldr r7, [r6]
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and r7, r7, r8
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orr r7, r7, $0x03
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str r7, [r6]
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/* Enable the Power Domain Transition Command */
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ldr r6, PTCMD
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ldr r7, [r6]
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orr r7, r7, $0x01
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str r7, [r6]
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/* Check for Transition Complete(PTSTAT) */
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checkStatClkStop:
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ldr r6, PTSTAT
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ldr r7, [r6]
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ands r7, r7, $0x01
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bne checkStatClkStop
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/* Check for DDR2 Controller Enable Completion */
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checkDDRStatClkStop:
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ldr r6, MDSTAT_DDR2
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ldr r7, [r6]
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and r7, r7, $MDSTAT_STATE
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cmp r7, $0x03
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bne checkDDRStatClkStop
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/*------------------------------------------------------*
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* Program DDR2 MMRs for 162MHz Setting *
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*------------------------------------------------------*/
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/* Program PHY Control Register */
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ldr r6, DDRCTL
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ldr r7, DDRCTL_VAL
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str r7, [r6]
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/* Program SDRAM Bank Config Register */
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ldr r6, SDCFG
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ldr r7, SDCFG_VAL
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str r7, [r6]
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/* Program SDRAM TIM-0 Config Register */
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ldr r6, SDTIM0
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ldr r7, SDTIM0_VAL_162MHz
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str r7, [r6]
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/* Program SDRAM TIM-1 Config Register */
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ldr r6, SDTIM1
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ldr r7, SDTIM1_VAL_162MHz
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str r7, [r6]
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/* Program the SDRAM Bank Config Control Register */
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ldr r10, MASK_VAL
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ldr r8, SDCFG
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ldr r9, SDCFG_VAL
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and r9, r9, r10
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str r9, [r8]
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/* Program SDRAM SDREF Config Register */
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ldr r6, SDREF
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ldr r7, SDREF_VAL
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str r7, [r6]
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/*------------------------------------------------------*
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* Issue Soft Reset to DDR Module *
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*------------------------------------------------------*/
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/* Issue a Dummy DDR2 read/write */
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ldr r8, DDR2_START_ADDR
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ldr r7, DUMMY_VAL
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str r7, [r8]
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ldr r7, [r8]
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/* Shut down the DDR2 LPSC Module */
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ldr r8, PSC_FLAG_CLEAR
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ldr r6, MDCTL_DDR2
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ldr r7, [r6]
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and r7, r7, r8
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orr r7, r7, $0x01
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str r7, [r6]
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/* Enable the Power Domain Transition Command */
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ldr r6, PTCMD
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ldr r7, [r6]
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orr r7, r7, $0x01
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str r7, [r6]
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/* Check for Transition Complete(PTSTAT) */
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checkStatClkStop2:
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ldr r6, PTSTAT
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ldr r7, [r6]
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ands r7, r7, $0x01
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bne checkStatClkStop2
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/* Check for DDR2 Controller Enable Completion */
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checkDDRStatClkStop2:
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ldr r6, MDSTAT_DDR2
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ldr r7, [r6]
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and r7, r7, $MDSTAT_STATE
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cmp r7, $0x01
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bne checkDDRStatClkStop2
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/*------------------------------------------------------*
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* Turn DDR2 Controller Clocks On *
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*------------------------------------------------------*/
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/* Enable the DDR2 LPSC Module */
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ldr r6, MDCTL_DDR2
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ldr r7, [r6]
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orr r7, r7, $0x03
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str r7, [r6]
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/* Enable the Power Domain Transition Command */
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ldr r6, PTCMD
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ldr r7, [r6]
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orr r7, r7, $0x01
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str r7, [r6]
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/* Check for Transition Complete(PTSTAT) */
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checkStatClkEn2:
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ldr r6, PTSTAT
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ldr r7, [r6]
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ands r7, r7, $0x01
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bne checkStatClkEn2
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/* Check for DDR2 Controller Enable Completion */
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checkDDRStatClkEn2:
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ldr r6, MDSTAT_DDR2
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ldr r7, [r6]
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and r7, r7, $MDSTAT_STATE
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cmp r7, $0x03
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bne checkDDRStatClkEn2
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/* DDR Writes and Reads */
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ldr r6, CFGTEST
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mov r3, $0x01
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str r3, [r6]
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/*------------------------------------------------------*
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* System PLL Initialization *
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*------------------------------------------------------*/
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/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
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mov r2, $0
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ldr r6, PLL1_CTL
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ldr r7, PLL_CLKSRC_MASK
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ldr r8, [r6]
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and r8, r8, r7
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mov r9, r2, lsl $8
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orr r8, r8, r9
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str r8, [r6]
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/* Select the PLLEN source */
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ldr r7, PLL_ENSRC_MASK
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and r8, r8, r7
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str r8, [r6]
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/* Bypass the PLL */
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ldr r7, PLL_BYPASS_MASK
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and r8, r8, r7
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str r8, [r6]
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/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
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mov r10, $0x20
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WaitLoop:
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subs r10, r10, $1
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bne WaitLoop
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/* Reset the PLL */
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ldr r7, PLL_RESET_MASK
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and r8, r8, r7
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str r8, [r6]
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/* Disable the PLL */
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orr r8, r8, $0x10
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str r8, [r6]
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/* Power up the PLL */
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ldr r7, PLL_PWRUP_MASK
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and r8, r8, r7
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str r8, [r6]
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/* Enable the PLL from Disable Mode */
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ldr r7, PLL_DISABLE_ENABLE_MASK
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and r8, r8, r7
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str r8, [r6]
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/* Program the PLL Multiplier */
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ldr r6, PLL1_PLLM
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mov r3, $0x15 /* For 594MHz */
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str r3, [r6]
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/* Wait for PLL to Reset Properly */
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mov r10, $0xff
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ResetLoop:
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subs r10, r10, $1
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bne ResetLoop
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/* Bring PLL out of Reset */
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ldr r6, PLL1_CTL
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orr r8, r8, $0x08
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str r8, [r6]
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/* Wait for PLL to Lock */
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ldr r10, PLL_LOCK_COUNT
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PLL1Lock:
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subs r10, r10, $1
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bne PLL1Lock
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/* Enable the PLL */
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orr r8, r8, $0x01
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str r8, [r6]
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nop
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nop
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nop
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nop
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/*------------------------------------------------------*
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* AEMIF configuration for NOR Flash (double check) *
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*------------------------------------------------------*/
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ldr r0, _PINMUX0
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ldr r1, _DEV_SETTING
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str r1, [r0]
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ldr r0, WAITCFG
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ldr r1, WAITCFG_VAL
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ldr r2, [r0]
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orr r2, r2, r1
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str r2, [r0]
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ldr r0, ACFG3
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ldr r1, ACFG3_VAL
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ldr r2, [r0]
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and r1, r2, r1
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str r1, [r0]
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ldr r0, ACFG4
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ldr r1, ACFG4_VAL
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ldr r2, [r0]
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and r1, r2, r1
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str r1, [r0]
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ldr r0, ACFG5
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ldr r1, ACFG5_VAL
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ldr r2, [r0]
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and r1, r2, r1
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str r1, [r0]
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/*--------------------------------------*
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* VTP manual Calibration *
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*--------------------------------------*/
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ldr r0, VTPIOCR
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ldr r1, VTP_MMR0
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str r1, [r0]
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ldr r0, VTPIOCR
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ldr r1, VTP_MMR1
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str r1, [r0]
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/* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
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ldr r10, VTP_LOCK_COUNT
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VTPLock:
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subs r10, r10, $1
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bne VTPLock
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ldr r6, DFT_ENABLE
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mov r10, $0x01
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str r10, [r6]
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ldr r6, DDRVTPR
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ldr r7, [r6]
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mov r8, r7, LSL #32-10
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mov r8, r8, LSR #32-10 /* grab low 10 bits */
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ldr r7, VTP_RECAL
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orr r8, r7, r8
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ldr r7, VTP_EN
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orr r8, r7, r8
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str r8, [r0]
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/* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
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ldr r10, VTP_LOCK_COUNT
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VTP1Lock:
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subs r10, r10, $1
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bne VTP1Lock
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ldr r1, [r0]
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ldr r2, VTP_MASK
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and r2, r1, r2
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str r2, [r0]
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ldr r6, DFT_ENABLE
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mov r10, $0
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str r10, [r6]
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/*
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* Call board-specific lowlevel init.
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* That MUST be present and THAT returns
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* back to arch calling code with "mov pc, lr."
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*/
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b dv_board_init
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.ltorg
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_PINMUX0:
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.word 0x01c40000 /* Device Configuration Registers */
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_PINMUX1:
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.word 0x01c40004 /* Device Configuration Registers */
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_DEV_SETTING:
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.word 0x00000c1f
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WAITCFG:
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.word 0x01e00004
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WAITCFG_VAL:
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.word 0
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ACFG3:
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.word 0x01e00014
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ACFG3_VAL:
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.word 0x3ffffffd
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ACFG4:
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.word 0x01e00018
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|
ACFG4_VAL:
|
|
.word 0x3ffffffd
|
|
ACFG5:
|
|
.word 0x01e0001c
|
|
ACFG5_VAL:
|
|
.word 0x3ffffffd
|
|
|
|
MDCTL_DDR2:
|
|
.word 0x01c41a34
|
|
MDSTAT_DDR2:
|
|
.word 0x01c41834
|
|
|
|
PTCMD:
|
|
.word 0x01c41120
|
|
PTSTAT:
|
|
.word 0x01c41128
|
|
|
|
EINT_ENABLE0:
|
|
.word 0x01c48018
|
|
EINT_ENABLE1:
|
|
.word 0x01c4801c
|
|
|
|
PSC_FLAG_CLEAR:
|
|
.word 0xffffffe0
|
|
PSC_GEM_FLAG_CLEAR:
|
|
.word 0xfffffeff
|
|
|
|
/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
|
|
DDRCTL:
|
|
.word 0x200000e4
|
|
DDRCTL_VAL:
|
|
.word 0x50006405
|
|
SDREF:
|
|
.word 0x2000000c
|
|
SDREF_VAL:
|
|
.word 0x000005c3
|
|
SDCFG:
|
|
.word 0x20000008
|
|
SDCFG_VAL:
|
|
#ifdef DDR_4BANKS
|
|
.word 0x00178622
|
|
#elif defined DDR_8BANKS
|
|
.word 0x00178632
|
|
#else
|
|
#error "Unknown DDR configuration!!!"
|
|
#endif
|
|
SDTIM0:
|
|
.word 0x20000010
|
|
SDTIM0_VAL_162MHz:
|
|
.word 0x28923211
|
|
SDTIM1:
|
|
.word 0x20000014
|
|
SDTIM1_VAL_162MHz:
|
|
.word 0x0016c722
|
|
VTPIOCR:
|
|
.word 0x200000f0 /* VTP IO Control register */
|
|
DDRVTPR:
|
|
.word 0x01c42030 /* DDR VPTR MMR */
|
|
VTP_MMR0:
|
|
.word 0x201f
|
|
VTP_MMR1:
|
|
.word 0xa01f
|
|
DFT_ENABLE:
|
|
.word 0x01c4004c
|
|
VTP_LOCK_COUNT:
|
|
.word 0x5b0
|
|
VTP_MASK:
|
|
.word 0xffffdfff
|
|
VTP_RECAL:
|
|
.word 0x08000
|
|
VTP_EN:
|
|
.word 0x02000
|
|
CFGTEST:
|
|
.word 0x80010000
|
|
MASK_VAL:
|
|
.word 0x00000fff
|
|
|
|
/* GEM Power Up & LPSC Control Register */
|
|
MDCTL_GEM:
|
|
.word 0x01c41a9c
|
|
MDSTAT_GEM:
|
|
.word 0x01c4189c
|
|
|
|
/* For WDT reset chip bug */
|
|
P1394:
|
|
.word 0x01c41a20
|
|
|
|
PLL_CLKSRC_MASK:
|
|
.word 0xfffffeff /* Mask the Clock Mode bit */
|
|
PLL_ENSRC_MASK:
|
|
.word 0xffffffdf /* Select the PLLEN source */
|
|
PLL_BYPASS_MASK:
|
|
.word 0xfffffffe /* Put the PLL in BYPASS */
|
|
PLL_RESET_MASK:
|
|
.word 0xfffffff7 /* Put the PLL in Reset Mode */
|
|
PLL_PWRUP_MASK:
|
|
.word 0xfffffffd /* PLL Power up Mask Bit */
|
|
PLL_DISABLE_ENABLE_MASK:
|
|
.word 0xffffffef /* Enable the PLL from Disable */
|
|
PLL_LOCK_COUNT:
|
|
.word 0x2000
|
|
|
|
/* PLL1-SYSTEM PLL MMRs */
|
|
PLL1_CTL:
|
|
.word 0x01c40900
|
|
PLL1_PLLM:
|
|
.word 0x01c40910
|
|
|
|
/* PLL2-SYSTEM PLL MMRs */
|
|
PLL2_CTL:
|
|
.word 0x01c40d00
|
|
PLL2_PLLM:
|
|
.word 0x01c40d10
|
|
PLL2_DIV1:
|
|
.word 0x01c40d18
|
|
PLL2_DIV2:
|
|
.word 0x01c40d1c
|
|
PLL2_PLLCMD:
|
|
.word 0x01c40d38
|
|
PLL2_PLLSTAT:
|
|
.word 0x01c40d3c
|
|
PLL2_DIV_MASK:
|
|
.word 0xffff7fff
|
|
|
|
MMARG_BRF0:
|
|
.word 0x01c42010 /* BRF margin mode 0 (R/W)*/
|
|
MMARG_BRF0_VAL:
|
|
.word 0x00444400
|
|
|
|
DDR2_START_ADDR:
|
|
.word 0x80000000
|
|
DUMMY_VAL:
|
|
.word 0xa55aa55a
|
|
#else /* CONFIG_SOC_DM644X */
|
|
mov pc, lr
|
|
#endif
|