170 lines
4.1 KiB
Plaintext
170 lines
4.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,luton";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart0;
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};
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sys_clk: sys-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <208333333>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x60000000 0x10200000>;
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uart0: serial@10100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x10100000 0x20>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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gpio: pinctrl@70068 {
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compatible = "mscc,luton-pinctrl";
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reg = <0x70068 0x68>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 32>;
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sgpio_pins: sgpio-pins {
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pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
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function = "sio";
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};
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uart_pins: uart-pins {
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pins = "GPIO_30", "GPIO_31";
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function = "uart";
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};
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};
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sgpio: gpio@70130 {
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compatible = "mscc,luton-sgpio";
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status = "disabled";
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clocks = <&sys_clk>;
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pinctrl-0 = <&sgpio_pins>;
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pinctrl-names = "default";
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reg = <0x0070130 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&sgpio 0 0 64>;
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};
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spi0: spi-bitbang {
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compatible = "mscc,luton-bb-spi";
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status = "okay";
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reg = <0x10000064 0x4>;
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num-chipselects = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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switch: switch@1010000 {
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compatible = "mscc,vsc7527-switch";
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reg = <0x1e0000 0x0100>, // VTSS_TO_DEV_0
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<0x1f0000 0x0100>, // VTSS_TO_DEV_1
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<0x200000 0x0100>, // VTSS_TO_DEV_2
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<0x210000 0x0100>, // VTSS_TO_DEV_3
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<0x220000 0x0100>, // VTSS_TO_DEV_4
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<0x230000 0x0100>, // VTSS_TO_DEV_5
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<0x240000 0x0100>, // VTSS_TO_DEV_6
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<0x250000 0x0100>, // VTSS_TO_DEV_7
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<0x260000 0x0100>, // VTSS_TO_DEV_8
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<0x270000 0x0100>, // VTSS_TO_DEV_9
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<0x280000 0x0100>, // VTSS_TO_DEV_10
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<0x290000 0x0100>, // VTSS_TO_DEV_11
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<0x2a0000 0x0100>, // VTSS_TO_DEV_12
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<0x2b0000 0x0100>, // VTSS_TO_DEV_13
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<0x2c0000 0x0100>, // VTSS_TO_DEV_14
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<0x2d0000 0x0100>, // VTSS_TO_DEV_15
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<0x2e0000 0x0100>, // VTSS_TO_DEV_16
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<0x2f0000 0x0100>, // VTSS_TO_DEV_17
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<0x300000 0x0100>, // VTSS_TO_DEV_18
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<0x310000 0x0100>, // VTSS_TO_DEV_19
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<0x320000 0x0100>, // VTSS_TO_DEV_20
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<0x330000 0x0100>, // VTSS_TO_DEV_21
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<0x340000 0x0100>, // VTSS_TO_DEV_22
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<0x350000 0x0100>, // VTSS_TO_DEV_23
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<0x010000 0x1000>, // VTSS_TO_SYS
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<0x020000 0x1000>, // VTSS_TO_ANA
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<0x030000 0x1000>, // VTSS_TO_REW
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<0x070000 0x1000>, // VTSS_TO_DEVCPU_GCB
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<0x080000 0x0100>, // VTSS_TO_DEVCPU_QS
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<0x0a0000 0x10000>; // VTSS_TO_HSIO
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reg-names = "port0", "port1", "port2", "port3",
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"port4", "port5", "port6", "port7",
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"port8", "port9", "port10", "port11",
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"port12", "port13", "port14", "port15",
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"port16", "port17", "port18", "port19",
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"port20", "port21", "port22", "port23",
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"sys", "ana", "rew", "gcb", "qs", "hsio";
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status = "okay";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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mdio0: mdio@700a0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,luton-miim";
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reg = <0x700a0 0x24>;
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status = "disabled";
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};
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mdio1: mdio@700c4 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,luton-miim";
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reg = <0x700c4 0x24>;
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status = "disabled";
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};
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hsio: syscon@10d0000 {
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compatible = "mscc,luton-hsio", "syscon", "simple-mfd";
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reg = <0xa0000 0x10000>;
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serdes_hsio: serdes_hsio {
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compatible = "mscc,vsc7527-serdes";
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#phy-cells = <3>;
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};
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};
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};
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};
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