86 lines
1.9 KiB
C
86 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <ram.h>
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#include <wdt.h>
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#include <asm/io.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include "mt76xx.h"
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#define STR_LEN 6
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#ifdef CONFIG_BOOT_ROM
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int mach_cpu_init(void)
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{
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ddr_calibrate();
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return 0;
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}
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#endif
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M);
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return 0;
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}
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int print_cpuinfo(void)
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{
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static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)",
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"PLL (4-Byte SPI Addr)",
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"XTAL (3-Byte SPI Addr)",
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"XTAL (4-Byte SPI Addr)" };
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const void *blob = gd->fdt_blob;
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void __iomem *sysc_base;
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char buf[STR_LEN + 1];
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fdt_addr_t base;
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fdt_size_t size;
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char *str;
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int node;
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u32 val;
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/* Get system controller base address */
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node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc");
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if (node < 0)
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return -FDT_ERR_NOTFOUND;
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base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg",
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0, &size, true);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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sysc_base = ioremap_nocache(base, size);
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str = (char *)sysc_base + MT76XX_CHIPID_OFFS;
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snprintf(buf, STR_LEN + 1, "%s", str);
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val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS);
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printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf,
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(val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0));
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val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1;
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printf("Boot from %s\n", boot_str[val]);
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return 0;
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}
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int arch_misc_init(void)
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{
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/*
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* It has been noticed, that sometimes the d-cache is not in a
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* "clean-state" when U-Boot is running on MT7688. This was
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* detected when using the ethernet driver (which uses d-cache)
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* and a TFTP command does not complete. Flushing the complete
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* d-cache (again?) here seems to fix this issue.
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*/
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flush_dcache_range(gd->bd->bi_memstart,
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gd->bd->bi_memstart + gd->ram_size - 1);
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return 0;
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}
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