207 lines
6.2 KiB
C
207 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <asm/acpi_s3.h>
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#include <asm/acpi_table.h>
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#include <asm/io.h>
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#include <asm/tables.h>
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#include <asm/arch/global_nvs.h>
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#include <asm/arch/iomap.h>
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void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
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void *dsdt)
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{
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struct acpi_table_header *header = &(fadt->header);
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u16 pmbase = ACPI_BASE_ADDRESS;
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memset((void *)fadt, 0, sizeof(struct acpi_fadt));
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acpi_fill_header(header, "FACP");
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header->length = sizeof(struct acpi_fadt);
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header->revision = 4;
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fadt->firmware_ctrl = (u32)facs;
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fadt->dsdt = (u32)dsdt;
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fadt->preferred_pm_profile = ACPI_PM_MOBILE;
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fadt->sci_int = 9;
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fadt->smi_cmd = 0;
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fadt->acpi_enable = 0;
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fadt->acpi_disable = 0;
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fadt->s4bios_req = 0;
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fadt->pstate_cnt = 0;
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fadt->pm1a_evt_blk = pmbase;
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fadt->pm1b_evt_blk = 0x0;
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fadt->pm1a_cnt_blk = pmbase + 0x4;
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fadt->pm1b_cnt_blk = 0x0;
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fadt->pm2_cnt_blk = pmbase + 0x50;
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fadt->pm_tmr_blk = pmbase + 0x8;
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fadt->gpe0_blk = pmbase + 0x20;
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fadt->gpe1_blk = 0;
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 8;
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fadt->gpe1_blk_len = 0;
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fadt->gpe1_base = 0;
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fadt->cst_cnt = 0;
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
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fadt->flush_size = 0;
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fadt->flush_stride = 0;
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fadt->duty_offset = 1;
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fadt->duty_width = 0;
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fadt->day_alrm = 0x0d;
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fadt->mon_alrm = 0x00;
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fadt->century = 0x00;
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fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
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fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
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ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
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ACPI_FADT_PLATFORM_CLOCK;
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fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->reset_reg.bit_width = 8;
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fadt->reset_reg.bit_offset = 0;
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fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->reset_reg.addrl = IO_PORT_RESET;
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fadt->reset_reg.addrh = 0;
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fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
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fadt->x_firmware_ctl_l = (u32)facs;
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fadt->x_firmware_ctl_h = 0;
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fadt->x_dsdt_l = (u32)dsdt;
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fadt->x_dsdt_h = 0;
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1b_evt_blk.bit_width = 0;
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fadt->x_pm1b_evt_blk.bit_offset = 0;
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fadt->x_pm1b_evt_blk.access_size = 0;
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fadt->x_pm1b_evt_blk.addrl = 0x0;
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fadt->x_pm1b_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1b_cnt_blk.bit_width = 0;
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fadt->x_pm1b_cnt_blk.bit_offset = 0;
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fadt->x_pm1b_cnt_blk.access_size = 0;
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fadt->x_pm1b_cnt_blk.addrl = 0x0;
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fadt->x_pm1b_cnt_blk.addrh = 0x0;
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fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
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fadt->x_pm2_cnt_blk.bit_offset = 0;
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fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
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fadt->x_pm2_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
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fadt->x_gpe0_blk.addrh = 0x0;
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fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe1_blk.bit_width = 0;
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fadt->x_gpe1_blk.bit_offset = 0;
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fadt->x_gpe1_blk.access_size = 0;
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fadt->x_gpe1_blk.addrl = 0x0;
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fadt->x_gpe1_blk.addrh = 0x0;
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header->checksum = table_compute_checksum(fadt, header->length);
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}
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void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
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{
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struct udevice *dev;
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int ret;
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/* at least we have one processor */
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gnvs->pcnt = 1;
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/* override the processor count with actual number */
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ret = uclass_find_first_device(UCLASS_CPU, &dev);
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if (ret == 0 && dev != NULL) {
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ret = cpu_get_count(dev);
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if (ret > 0)
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gnvs->pcnt = ret;
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}
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/* determine whether internal uart is on */
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if (IS_ENABLED(CONFIG_INTERNAL_UART))
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gnvs->iuart_en = 1;
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else
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gnvs->iuart_en = 0;
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}
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#ifdef CONFIG_HAVE_ACPI_RESUME
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/*
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* The following two routines are called at a very early stage, even before
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* FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS
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* and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses
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* of these two blocks are programmed by either U-Boot or FSP.
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*
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* It has been verified that 1st phase API (see arch/x86/lib/fsp/fsp_car.S)
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* on Intel BayTrail SoC already initializes these two base addresses so
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* we are safe to access these registers here.
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*/
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enum acpi_sleep_state chipset_prev_sleep_state(void)
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{
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u32 pm1_sts;
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u32 pm1_cnt;
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u32 gen_pmcon1;
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enum acpi_sleep_state prev_sleep_state = ACPI_S0;
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/* Read Power State */
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pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1);
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debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
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pm1_sts, pm1_cnt, gen_pmcon1);
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if (pm1_sts & WAK_STS)
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prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt);
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if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR))
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prev_sleep_state = ACPI_S5;
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return prev_sleep_state;
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}
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void chipset_clear_sleep_state(void)
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{
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u32 pm1_cnt;
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pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
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}
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#endif
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