109 lines
2.0 KiB
C
109 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* Based on code from coreboot src/soc/intel/broadwell/cpu.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <cpu.h>
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#include <asm/cpu.h>
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#include <asm/cpu_x86.h>
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#include <asm/cpu_common.h>
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#include <asm/intel_regs.h>
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#include <asm/lpc_common.h>
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#include <asm/msr.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/turbo.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/rcb.h>
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int arch_cpu_init_dm(void)
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{
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struct udevice *dev;
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int ret;
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/* Start up the LPC so we have serial */
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ret = uclass_first_device(UCLASS_LPC, &dev);
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if (ret)
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return ret;
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if (!dev)
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return -ENODEV;
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ret = cpu_set_flex_ratio_to_tdp_nominal();
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if (ret)
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return ret;
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return 0;
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}
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void set_max_freq(void)
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{
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msr_t msr, perf_ctl, platform_info;
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/* Check for configurable TDP option */
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platform_info = msr_read(MSR_PLATFORM_INFO);
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if ((platform_info.hi >> 1) & 3) {
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/* Set to nominal TDP ratio */
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msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
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perf_ctl.lo = (msr.lo & 0xff) << 8;
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} else {
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/* Platform Info bits 15:8 give max ratio */
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msr = msr_read(MSR_PLATFORM_INFO);
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perf_ctl.lo = msr.lo & 0xff00;
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}
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perf_ctl.hi = 0;
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msr_write(IA32_PERF_CTL, perf_ctl);
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debug("CPU: frequency set to %d MHz\n",
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((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
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}
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int arch_cpu_init(void)
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{
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post_code(POST_CPU_INIT);
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return x86_cpu_init_f();
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}
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int checkcpu(void)
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{
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int ret;
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set_max_freq();
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ret = cpu_common_init();
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if (ret)
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return ret;
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gd->arch.pei_boot_mode = PEI_BOOT_NONE;
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return 0;
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}
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int print_cpuinfo(void)
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{
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char processor_name[CPU_MAX_NAME_LEN];
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const char *name;
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/* Print processor name */
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name = cpu_get_name(processor_name);
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printf("CPU: %s\n", name);
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return 0;
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}
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void board_debug_uart_init(void)
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{
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struct udevice *bus = NULL;
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/* com1 / com2 decode range */
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pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
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pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
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PCI_SIZE_16);
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}
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