163 lines
3.7 KiB
C
163 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* (C) Copyright 2004
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* ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*/
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#include <common.h>
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#include <div64.h>
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#ifdef CONFIG_ARCH_CINTEGRATOR
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#define DIV_CLOCK_INIT 1
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#define TIMER_LOAD_VAL 0xFFFFFFFFL
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#else
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#define DIV_CLOCK_INIT 256
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#define TIMER_LOAD_VAL 0x0000FFFFL
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#endif
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/* The Integrator/CP timer1 is clocked at 1MHz
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* can be divided by 16 or 256
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* and can be set up as a 32-bit timer
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*/
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/* U-Boot expects a 32 bit timer, running at CONFIG_SYS_HZ */
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/* Keep total timer count to avoid losing decrements < div_timer */
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static unsigned long long total_count = 0;
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static unsigned long long lastdec; /* Timer reading at last call */
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/* Divisor applied to timer clock */
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static unsigned long long div_clock = DIV_CLOCK_INIT;
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static unsigned long long div_timer = 1; /* Divisor to convert timer reading
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* change to U-Boot ticks
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*/
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/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
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static ulong timestamp; /* U-Boot ticks since startup */
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#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
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/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
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* - unless otherwise stated
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*/
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/* starts up a counter
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* - the Integrator/CP timer can be set up to issue an interrupt */
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int timer_init (void)
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{
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/* Load timer with initial value */
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*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
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#ifdef CONFIG_ARCH_CINTEGRATOR
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/* Set timer to be
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* enabled 1
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* periodic 1
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* no interrupts 0
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* X 0
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* divider 1 00 == less rounding error
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* 32 bit 1
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* wrapping 0
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*/
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*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
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#else
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/* Set timer to be
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* enabled 1
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* free-running 0
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* XX 00
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* divider 256 10
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* XX 00
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*/
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*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
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#endif
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/* init the timestamp */
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total_count = 0ULL;
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/* capure current decrementer value */
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lastdec = READ_TIMER;
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/* start "advancing" time stamp from 0 */
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timestamp = 0L;
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div_timer = CONFIG_SYS_HZ_CLOCK;
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do_div(div_timer, CONFIG_SYS_HZ);
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do_div(div_timer, div_clock);
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return (0);
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}
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/*
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* timer without interrupts
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*/
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/* converts the timer reading to U-Boot ticks */
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/* the timestamp is the number of ticks since reset */
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static ulong get_timer_masked (void)
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{
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/* get current count */
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unsigned long long now = READ_TIMER;
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if(now > lastdec) {
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/* Must have wrapped */
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total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
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} else {
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total_count += lastdec - now;
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}
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lastdec = now;
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/* Reuse "now" */
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now = total_count;
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do_div(now, div_timer);
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timestamp = now;
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return timestamp;
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}
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ulong get_timer (ulong base_ticks)
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{
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return get_timer_masked () - base_ticks;
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}
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/* delay usec useconds */
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void __udelay (unsigned long usec)
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{
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ulong tmo, tmp;
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/* Convert to U-Boot ticks */
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tmo = usec * CONFIG_SYS_HZ;
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tmo /= (1000000L);
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tmp = get_timer_masked(); /* get current timestamp */
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tmo += tmp; /* form target timestamp */
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while (get_timer_masked () < tmo) {/* loop till event */
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/*NOP*/;
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}
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* Return the timebase clock frequency
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* i.e. how often the timer decrements
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*/
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ulong get_tbclk (void)
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{
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unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
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do_div(tmp, div_clock);
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return tmp;
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}
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