156 lines
3.6 KiB
C
156 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>
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*
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* Originally based on the Linux kernel v4.16 drivers/regulator/stm32-vrefbuf.c
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <power/regulator.h>
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/* STM32 VREFBUF registers */
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#define STM32_VREFBUF_CSR 0x00
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/* STM32 VREFBUF CSR bitfields */
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#define STM32_VRS GENMASK(6, 4)
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#define STM32_VRS_SHIFT 4
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#define STM32_VRR BIT(3)
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#define STM32_HIZ BIT(1)
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#define STM32_ENVR BIT(0)
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struct stm32_vrefbuf {
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void __iomem *base;
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struct clk clk;
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struct udevice *vdda_supply;
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};
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static const unsigned int stm32_vrefbuf_voltages[] = {
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/* Matches resp. VRS = 000b, 001b, 010b, 011b */
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2500000, 2048000, 1800000, 1500000,
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};
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static int stm32_vrefbuf_set_enable(struct udevice *dev, bool enable)
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{
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struct stm32_vrefbuf *priv = dev_get_priv(dev);
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u32 val;
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int ret;
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clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_HIZ | STM32_ENVR,
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enable ? STM32_ENVR : STM32_HIZ);
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if (!enable)
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return 0;
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/*
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* Vrefbuf startup time depends on external capacitor: wait here for
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* VRR to be set. That means output has reached expected value.
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* ~650us sleep should be enough for caps up to 1.5uF. Use 10ms as
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* arbitrary timeout.
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*/
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ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val,
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val & STM32_VRR, 10000);
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if (ret < 0) {
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dev_err(dev, "stm32 vrefbuf timed out: %d\n", ret);
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clrsetbits_le32(priv->base + STM32_VREFBUF_CSR, STM32_ENVR,
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STM32_HIZ);
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return ret;
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}
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return 0;
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}
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static int stm32_vrefbuf_get_enable(struct udevice *dev)
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{
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struct stm32_vrefbuf *priv = dev_get_priv(dev);
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return readl(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR;
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}
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static int stm32_vrefbuf_set_value(struct udevice *dev, int uV)
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{
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struct stm32_vrefbuf *priv = dev_get_priv(dev);
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(stm32_vrefbuf_voltages); i++) {
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if (uV == stm32_vrefbuf_voltages[i]) {
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clrsetbits_le32(priv->base + STM32_VREFBUF_CSR,
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STM32_VRS, i << STM32_VRS_SHIFT);
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return 0;
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}
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}
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return -EINVAL;
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}
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static int stm32_vrefbuf_get_value(struct udevice *dev)
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{
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struct stm32_vrefbuf *priv = dev_get_priv(dev);
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u32 val;
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val = readl(priv->base + STM32_VREFBUF_CSR) & STM32_VRS;
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val >>= STM32_VRS_SHIFT;
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return stm32_vrefbuf_voltages[val];
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}
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static const struct dm_regulator_ops stm32_vrefbuf_ops = {
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.get_value = stm32_vrefbuf_get_value,
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.set_value = stm32_vrefbuf_set_value,
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.get_enable = stm32_vrefbuf_get_enable,
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.set_enable = stm32_vrefbuf_set_enable,
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};
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static int stm32_vrefbuf_probe(struct udevice *dev)
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{
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struct stm32_vrefbuf *priv = dev_get_priv(dev);
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int ret;
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priv->base = dev_read_addr_ptr(dev);
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret) {
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dev_err(dev, "Can't get clock: %d\n", ret);
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return ret;
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}
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ret = clk_enable(&priv->clk);
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if (ret) {
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dev_err(dev, "Can't enable clock: %d\n", ret);
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return ret;
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}
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ret = device_get_supply_regulator(dev, "vdda-supply",
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&priv->vdda_supply);
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if (ret) {
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dev_dbg(dev, "No vdda-supply: %d\n", ret);
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return 0;
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}
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ret = regulator_set_enable(priv->vdda_supply, true);
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if (ret) {
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dev_err(dev, "Can't enable vdda-supply: %d\n", ret);
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clk_disable(&priv->clk);
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}
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return ret;
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}
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static const struct udevice_id stm32_vrefbuf_ids[] = {
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{ .compatible = "st,stm32-vrefbuf" },
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{ }
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};
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U_BOOT_DRIVER(stm32_vrefbuf) = {
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.name = "stm32-vrefbuf",
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.id = UCLASS_REGULATOR,
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.of_match = stm32_vrefbuf_ids,
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.probe = stm32_vrefbuf_probe,
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.ops = &stm32_vrefbuf_ops,
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.priv_auto_alloc_size = sizeof(struct stm32_vrefbuf),
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};
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