440 lines
11 KiB
C
440 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 Cisco Systems, Inc.
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*
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
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*/
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#include <asm/io.h>
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#include <command.h>
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#include <config.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <log.h>
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#include <malloc.h>
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#include <spi.h>
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#include <time.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define SPBR_MIN 8
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#define BITS_PER_WORD 8
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#define NUM_TXRAM 32
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#define NUM_RXRAM 32
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#define NUM_CDRAM 16
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/* hif_mspi register structure. */
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struct bcmstb_hif_mspi_regs {
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u32 spcr0_lsb; /* 0x000 */
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u32 spcr0_msb; /* 0x004 */
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u32 spcr1_lsb; /* 0x008 */
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u32 spcr1_msb; /* 0x00c */
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u32 newqp; /* 0x010 */
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u32 endqp; /* 0x014 */
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u32 spcr2; /* 0x018 */
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u32 reserved0; /* 0x01c */
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u32 mspi_status; /* 0x020 */
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u32 cptqp; /* 0x024 */
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u32 spcr3; /* 0x028 */
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u32 revision; /* 0x02c */
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u32 reserved1[4]; /* 0x030 */
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u32 txram[NUM_TXRAM]; /* 0x040 */
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u32 rxram[NUM_RXRAM]; /* 0x0c0 */
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u32 cdram[NUM_CDRAM]; /* 0x140 */
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u32 write_lock; /* 0x180 */
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};
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/* hif_mspi masks. */
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#define HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK 0x00000080
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#define HIF_MSPI_SPCR2_SPE_MASK 0x00000040
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#define HIF_MSPI_SPCR2_SPIFIE_MASK 0x00000020
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#define HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK 0x00000001
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/* bspi offsets. */
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#define BSPI_MAST_N_BOOT_CTRL 0x008
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/* bspi_raf is not used in this driver. */
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/* hif_spi_intr2 offsets and masks. */
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#define HIF_SPI_INTR2_CPU_CLEAR 0x08
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#define HIF_SPI_INTR2_CPU_MASK_SET 0x10
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#define HIF_SPI_INTR2_CPU_MASK_CLEAR 0x14
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#define HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK 0x00000020
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/* SPI transfer timeout in milliseconds. */
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#define HIF_MSPI_WAIT 10
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enum bcmstb_base_type {
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HIF_MSPI,
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BSPI,
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HIF_SPI_INTR2,
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CS_REG,
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BASE_LAST,
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};
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struct bcmstb_spi_platdata {
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void *base[4];
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};
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struct bcmstb_spi_priv {
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struct bcmstb_hif_mspi_regs *regs;
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void *bspi;
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void *hif_spi_intr2;
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void *cs_reg;
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int default_cs;
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int curr_cs;
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uint tx_slot;
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uint rx_slot;
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u8 saved_cmd[NUM_CDRAM];
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uint saved_cmd_len;
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void *saved_din_addr;
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};
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static int bcmstb_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct bcmstb_spi_platdata *plat = dev_get_platdata(bus);
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const void *fdt = gd->fdt_blob;
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int node = dev_of_offset(bus);
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int ret = 0;
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int i = 0;
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struct fdt_resource resource = { 0 };
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char *names[BASE_LAST] = { "hif_mspi", "bspi", "hif_spi_intr2",
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"cs_reg" };
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const phys_addr_t defaults[BASE_LAST] = { BCMSTB_HIF_MSPI_BASE,
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BCMSTB_BSPI_BASE,
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BCMSTB_HIF_SPI_INTR2,
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BCMSTB_CS_REG };
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for (i = 0; i < BASE_LAST; i++) {
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plat->base[i] = (void *)defaults[i];
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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names[i], &resource);
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if (ret) {
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printf("%s: Assuming BCMSTB SPI %s address 0x0x%p\n",
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__func__, names[i], (void *)defaults[i]);
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} else {
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plat->base[i] = (void *)resource.start;
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debug("BCMSTB SPI %s address: 0x0x%p\n",
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names[i], (void *)plat->base[i]);
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}
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}
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return 0;
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}
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static void bcmstb_spi_hw_set_parms(struct bcmstb_spi_priv *priv)
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{
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writel(SPBR_MIN, &priv->regs->spcr0_lsb);
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writel(BITS_PER_WORD << 2 | SPI_MODE_3, &priv->regs->spcr0_msb);
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}
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static void bcmstb_spi_enable_interrupt(void *base, u32 mask)
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{
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void *reg = base + HIF_SPI_INTR2_CPU_MASK_CLEAR;
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writel(readl(reg) | mask, reg);
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readl(reg);
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}
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static void bcmstb_spi_disable_interrupt(void *base, u32 mask)
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{
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void *reg = base + HIF_SPI_INTR2_CPU_MASK_SET;
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writel(readl(reg) | mask, reg);
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readl(reg);
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}
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static void bcmstb_spi_clear_interrupt(void *base, u32 mask)
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{
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void *reg = base + HIF_SPI_INTR2_CPU_CLEAR;
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writel(readl(reg) | mask, reg);
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readl(reg);
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}
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static int bcmstb_spi_probe(struct udevice *bus)
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{
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struct bcmstb_spi_platdata *plat = dev_get_platdata(bus);
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struct bcmstb_spi_priv *priv = dev_get_priv(bus);
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priv->regs = plat->base[HIF_MSPI];
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priv->bspi = plat->base[BSPI];
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priv->hif_spi_intr2 = plat->base[HIF_SPI_INTR2];
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priv->cs_reg = plat->base[CS_REG];
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priv->default_cs = 0;
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priv->curr_cs = -1;
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priv->tx_slot = 0;
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priv->rx_slot = 0;
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memset(priv->saved_cmd, 0, NUM_CDRAM);
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priv->saved_cmd_len = 0;
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priv->saved_din_addr = NULL;
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debug("spi_xfer: tx regs: 0x%p\n", &priv->regs->txram[0]);
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debug("spi_xfer: rx regs: 0x%p\n", &priv->regs->rxram[0]);
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/* Disable BSPI. */
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writel(1, priv->bspi + BSPI_MAST_N_BOOT_CTRL);
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readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL);
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/* Set up interrupts. */
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bcmstb_spi_disable_interrupt(priv->hif_spi_intr2, 0xffffffff);
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bcmstb_spi_clear_interrupt(priv->hif_spi_intr2, 0xffffffff);
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bcmstb_spi_enable_interrupt(priv->hif_spi_intr2,
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HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK);
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/* Set up control registers. */
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writel(0, &priv->regs->spcr1_lsb);
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writel(0, &priv->regs->spcr1_msb);
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writel(0, &priv->regs->newqp);
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writel(0, &priv->regs->endqp);
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writel(HIF_MSPI_SPCR2_SPIFIE_MASK, &priv->regs->spcr2);
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writel(0, &priv->regs->spcr3);
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bcmstb_spi_hw_set_parms(priv);
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return 0;
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}
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static void bcmstb_spi_submit(struct bcmstb_spi_priv *priv, bool done)
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{
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debug("WR NEWQP: %d\n", 0);
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writel(0, &priv->regs->newqp);
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debug("WR ENDQP: %d\n", priv->tx_slot - 1);
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writel(priv->tx_slot - 1, &priv->regs->endqp);
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if (done) {
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debug("WR CDRAM[%d]: %02x\n", priv->tx_slot - 1,
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readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80);
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writel(readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80,
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&priv->regs->cdram[priv->tx_slot - 1]);
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}
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/* Force chip select first time. */
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if (priv->curr_cs != priv->default_cs) {
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debug("spi_xfer: switching chip select to %d\n",
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priv->default_cs);
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writel((readl(priv->cs_reg) & ~0xff) | (1 << priv->default_cs),
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priv->cs_reg);
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readl(priv->cs_reg);
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udelay(10);
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priv->curr_cs = priv->default_cs;
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}
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debug("WR WRITE_LOCK: %02x\n", 1);
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writel((readl(&priv->regs->write_lock) &
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~HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK) | 1,
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&priv->regs->write_lock);
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readl(&priv->regs->write_lock);
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debug("WR SPCR2: %02x\n",
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HIF_MSPI_SPCR2_SPIFIE_MASK |
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HIF_MSPI_SPCR2_SPE_MASK |
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HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK);
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writel(HIF_MSPI_SPCR2_SPIFIE_MASK |
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HIF_MSPI_SPCR2_SPE_MASK |
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HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK,
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&priv->regs->spcr2);
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}
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static int bcmstb_spi_wait(struct bcmstb_spi_priv *priv)
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{
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u32 start_time = get_timer(0);
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u32 status = readl(&priv->regs->mspi_status);
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while (!(status & 1)) {
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if (get_timer(start_time) > HIF_MSPI_WAIT)
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return -ETIMEDOUT;
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status = readl(&priv->regs->mspi_status);
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}
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writel(readl(&priv->regs->mspi_status) & ~1, &priv->regs->mspi_status);
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bcmstb_spi_clear_interrupt(priv->hif_spi_intr2,
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HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK);
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return 0;
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}
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static int bcmstb_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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uint len = bitlen / 8;
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uint tx_len = len;
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uint rx_len = len;
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const u8 *out_bytes = (u8 *)dout;
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u8 *in_bytes = (u8 *)din;
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struct udevice *bus = dev_get_parent(dev);
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struct bcmstb_spi_priv *priv = dev_get_priv(bus);
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struct bcmstb_hif_mspi_regs *regs = priv->regs;
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debug("spi_xfer: %d, t: 0x%p, r: 0x%p, f: %lx\n",
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len, dout, din, flags);
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debug("spi_xfer: chip select: %x\n", readl(priv->cs_reg) & 0xff);
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debug("spi_xfer: tx addr: 0x%p\n", ®s->txram[0]);
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debug("spi_xfer: rx addr: 0x%p\n", ®s->rxram[0]);
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debug("spi_xfer: cd addr: 0x%p\n", ®s->cdram[0]);
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if (flags & SPI_XFER_END) {
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debug("spi_xfer: clearing saved din address: 0x%p\n",
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priv->saved_din_addr);
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priv->saved_din_addr = NULL;
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priv->saved_cmd_len = 0;
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memset(priv->saved_cmd, 0, NUM_CDRAM);
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}
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if (bitlen == 0)
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return 0;
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if (bitlen % 8) {
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printf("%s: Non-byte-aligned transfer\n", __func__);
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return -EOPNOTSUPP;
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}
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if (flags & ~(SPI_XFER_BEGIN | SPI_XFER_END)) {
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printf("%s: Unsupported flags: %lx\n", __func__, flags);
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return -EOPNOTSUPP;
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}
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if (flags & SPI_XFER_BEGIN) {
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priv->tx_slot = 0;
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priv->rx_slot = 0;
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if (out_bytes && len > NUM_CDRAM) {
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printf("%s: Unable to save transfer\n", __func__);
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return -EOPNOTSUPP;
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}
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if (out_bytes && !(flags & SPI_XFER_END)) {
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/*
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* This is the start of a transmit operation
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* that will need repeating if the calling
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* code polls for the result. Save it for
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* subsequent transmission.
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*/
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debug("spi_xfer: saving command: %x, %d\n",
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out_bytes[0], len);
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priv->saved_cmd_len = len;
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memcpy(priv->saved_cmd, out_bytes, priv->saved_cmd_len);
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}
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}
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if (!(flags & (SPI_XFER_BEGIN | SPI_XFER_END))) {
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if (priv->saved_din_addr == din) {
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/*
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* The caller is polling for status. Repeat
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* the last transmission.
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*/
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int ret = 0;
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debug("spi_xfer: Making recursive call\n");
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ret = bcmstb_spi_xfer(dev, priv->saved_cmd_len * 8,
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priv->saved_cmd, NULL,
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SPI_XFER_BEGIN);
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if (ret) {
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printf("%s: Recursive call failed\n", __func__);
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return ret;
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}
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} else {
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debug("spi_xfer: saving din address: 0x%p\n", din);
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priv->saved_din_addr = din;
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}
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}
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while (rx_len > 0) {
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priv->rx_slot = priv->tx_slot;
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while (priv->tx_slot < NUM_CDRAM && tx_len > 0) {
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bcmstb_spi_hw_set_parms(priv);
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debug("WR TXRAM[%d]: %02x\n", priv->tx_slot,
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out_bytes ? out_bytes[len - tx_len] : 0xff);
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writel(out_bytes ? out_bytes[len - tx_len] : 0xff,
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®s->txram[priv->tx_slot << 1]);
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debug("WR CDRAM[%d]: %02x\n", priv->tx_slot, 0x8e);
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writel(0x8e, ®s->cdram[priv->tx_slot]);
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priv->tx_slot++;
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tx_len--;
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if (!in_bytes)
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rx_len--;
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}
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debug("spi_xfer: early return clauses: %d, %d, %d\n",
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len <= NUM_CDRAM,
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!in_bytes,
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(flags & (SPI_XFER_BEGIN |
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SPI_XFER_END)) == SPI_XFER_BEGIN);
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if (len <= NUM_CDRAM &&
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!in_bytes &&
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(flags & (SPI_XFER_BEGIN | SPI_XFER_END)) == SPI_XFER_BEGIN)
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return 0;
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bcmstb_spi_submit(priv, tx_len == 0);
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if (bcmstb_spi_wait(priv) == -ETIMEDOUT) {
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printf("%s: Timed out\n", __func__);
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return -ETIMEDOUT;
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}
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priv->tx_slot %= NUM_CDRAM;
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if (in_bytes) {
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while (priv->rx_slot < NUM_CDRAM && rx_len > 0) {
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in_bytes[len - rx_len] =
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readl(®s->rxram[(priv->rx_slot << 1)
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+ 1])
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& 0xff;
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debug("RD RXRAM[%d]: %02x\n",
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priv->rx_slot, in_bytes[len - rx_len]);
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priv->rx_slot++;
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rx_len--;
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}
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}
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}
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if (flags & SPI_XFER_END) {
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debug("WR WRITE_LOCK: %02x\n", 0);
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writel((readl(&priv->regs->write_lock) &
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~HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK) | 0,
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&priv->regs->write_lock);
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readl(&priv->regs->write_lock);
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}
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return 0;
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}
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static int bcmstb_spi_set_speed(struct udevice *dev, uint speed)
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{
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return 0;
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}
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static int bcmstb_spi_set_mode(struct udevice *dev, uint mode)
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{
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return 0;
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}
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static const struct dm_spi_ops bcmstb_spi_ops = {
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.xfer = bcmstb_spi_xfer,
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.set_speed = bcmstb_spi_set_speed,
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.set_mode = bcmstb_spi_set_mode,
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};
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static const struct udevice_id bcmstb_spi_id[] = {
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{ .compatible = "brcm,spi-brcmstb" },
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{ }
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};
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U_BOOT_DRIVER(bcmstb_spi) = {
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.name = "bcmstb_spi",
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.id = UCLASS_SPI,
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.of_match = bcmstb_spi_id,
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.ops = &bcmstb_spi_ops,
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.ofdata_to_platdata = bcmstb_spi_ofdata_to_platdata,
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.probe = bcmstb_spi_probe,
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.platdata_auto_alloc_size = sizeof(struct bcmstb_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct bcmstb_spi_priv),
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};
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