129 lines
3.8 KiB
C
129 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* EHCI HCD (Host Controller Driver) for USB.
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*
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* Copyright (C) 2013,2014 Renesas Electronics Corporation
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* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/ehci-rmobile.h>
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#include "ehci.h"
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#if defined(CONFIG_R8A7740)
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static u32 usb_base_address[] = {
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0xC6700000
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};
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#elif defined(CONFIG_R8A7790)
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static u32 usb_base_address[] = {
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0xEE080000, /* USB0 (EHCI) */
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0xEE0A0000, /* USB1 */
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0xEE0C0000, /* USB2 */
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};
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#elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
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defined(CONFIG_R8A7794)
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static u32 usb_base_address[] = {
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0xEE080000, /* USB0 (EHCI) */
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0xEE0C0000, /* USB1 */
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};
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#else
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#error rmobile EHCI USB driver not supported on this platform
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#endif
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int ehci_hcd_stop(int index)
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{
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int i;
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u32 base;
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struct ahbcom_pci_bridge *ahbcom_pci;
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base = usb_base_address[index];
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ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
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writel(0, &ahbcom_pci->ahb_bus_ctr);
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/* reset ehci */
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setbits_le32(base + EHCI_USBCMD, CMD_RESET);
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for (i = 100; i > 0; i--) {
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if (!(readl(base + EHCI_USBCMD) & CMD_RESET))
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break;
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udelay(100);
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}
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if (!i)
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printf("error : ehci(%d) reset failed.\n", index);
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if (index == (ARRAY_SIZE(usb_base_address) - 1))
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setbits_le32(SMSTPCR7, SMSTPCR703);
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return 0;
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}
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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u32 base;
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u32 phys_base;
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struct rmobile_ehci_reg *rehci;
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struct ahbcom_pci_bridge *ahbcom_pci;
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struct ahbconf_pci_bridge *ahbconf_pci;
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struct ahb_pciconf *ahb_pciconf_ohci;
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struct ahb_pciconf *ahb_pciconf_ehci;
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uint32_t cap_base;
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base = usb_base_address[index];
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phys_base = base;
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if (index == 0)
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clrbits_le32(SMSTPCR7, SMSTPCR703);
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rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET);
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ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
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ahbconf_pci =
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(struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET);
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ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET);
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ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET);
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/* Clock & Reset & Direct Power Down */
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clrsetbits_le32(&ahbcom_pci->usbctr,
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(DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB);
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clrbits_le32(&ahbcom_pci->usbctr, PLL_RST);
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/* AHB-PCI Bridge Communication Registers */
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writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
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writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
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&ahbcom_pci->pciahb_win1_ctr);
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writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
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&ahbcom_pci->pciahb_win2_ctr);
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writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr);
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setbits_le32(&ahbcom_pci->pci_arbiter_ctr,
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PCIBP_MODE | PCIREQ1 | PCIREQ0);
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/* PCI Configuration Registers for AHBPCI */
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writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
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&ahbcom_pci->ahbpci_win1_ctr);
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writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
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writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
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writel(0xf0000000, &ahbconf_pci->win2_basead);
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writel(SERREN | PERREN | MASTEREN | MEMEN,
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&ahbconf_pci->cmnd_sts);
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/* PCI Configuration Registers for EHCI */
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writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr);
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writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead);
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writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead);
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writel(SERREN | PERREN | MASTEREN | MEMEN,
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&ahb_pciconf_ohci->cmnd_sts);
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writel(SERREN | PERREN | MASTEREN | MEMEN,
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&ahb_pciconf_ehci->cmnd_sts);
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/* Enable PCI interrupt */
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setbits_le32(&ahbcom_pci->pci_int_enable,
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USBH_PMEEN | USBH_INTBEN | USBH_INTAEN);
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*hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion);
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cap_base = ehci_readl(&(*hccr)->cr_capbase);
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*hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base));
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return 0;
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}
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