120 lines
3.1 KiB
C
120 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* ARM Cortex M3/M4/M7 SysTick timer driver
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* (C) Copyright 2017 Renesas Electronics Europe Ltd
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*
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* Based on arch/arm/mach-stm32/stm32f1/timer.c
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* Copyright 2015 ATS Advanced Telematics Systems GmbH
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* Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
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*
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* The SysTick timer is a 24-bit count down timer. The clock can be either the
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* CPU clock or a reference clock. Since the timer will wrap around very quickly
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* when using the CPU clock, and we do not handle the timer interrupts, it is
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* expected that this driver is only ever used with a slow reference clock.
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*
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* The number of reference clock ticks that correspond to 10ms is normally
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* defined in the SysTick Calibration register's TENMS field. However, on some
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* devices this is wrong, so this driver allows the clock rate to be defined
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* using CONFIG_SYS_HZ_CLOCK.
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*/
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#include <common.h>
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#include <init.h>
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#include <time.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */
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#define SYSTICK_BASE 0xE000E010
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struct cm3_systick {
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uint32_t ctrl;
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uint32_t reload_val;
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uint32_t current_val;
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uint32_t calibration;
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};
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#define TIMER_MAX_VAL 0x00FFFFFF
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#define SYSTICK_CTRL_EN BIT(0)
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/* Clock source: 0 = Ref clock, 1 = CPU clock */
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#define SYSTICK_CTRL_CPU_CLK BIT(2)
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#define SYSTICK_CAL_NOREF BIT(31)
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#define SYSTICK_CAL_SKEW BIT(30)
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#define SYSTICK_CAL_TENMS_MASK 0x00FFFFFF
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/* read the 24-bit timer */
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static ulong read_timer(void)
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{
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struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
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/* The timer counts down, therefore convert to an incrementing timer */
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return TIMER_MAX_VAL - readl(&systick->current_val);
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}
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int timer_init(void)
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{
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struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
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u32 cal;
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writel(TIMER_MAX_VAL, &systick->reload_val);
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/* Any write to current_val reg clears it to 0 */
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writel(0, &systick->current_val);
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cal = readl(&systick->calibration);
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if (cal & SYSTICK_CAL_NOREF)
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/* Use CPU clock, no interrupts */
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writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, &systick->ctrl);
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else
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/* Use external clock, no interrupts */
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writel(SYSTICK_CTRL_EN, &systick->ctrl);
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/*
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* If the TENMS field is inexact or wrong, specify the clock rate using
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* CONFIG_SYS_HZ_CLOCK.
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*/
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#if defined(CONFIG_SYS_HZ_CLOCK)
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gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
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#else
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gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
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#endif
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gd->arch.tbl = 0;
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gd->arch.tbu = 0;
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gd->arch.lastinc = read_timer();
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return 0;
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}
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/* return milli-seconds timer value */
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ulong get_timer(ulong base)
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{
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unsigned long long t = get_ticks() * 1000;
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return (ulong)((t / gd->arch.timer_rate_hz)) - base;
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}
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unsigned long long get_ticks(void)
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{
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u32 now = read_timer();
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if (now >= gd->arch.lastinc)
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gd->arch.tbl += (now - gd->arch.lastinc);
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else
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gd->arch.tbl += (TIMER_MAX_VAL - gd->arch.lastinc) + now;
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gd->arch.lastinc = now;
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return gd->arch.tbl;
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}
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ulong get_tbclk(void)
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{
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return gd->arch.timer_rate_hz;
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}
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