89 lines
2.5 KiB
Plaintext
89 lines
2.5 KiB
Plaintext
menu "FPGA support"
|
|
|
|
config FPGA
|
|
bool
|
|
|
|
config FPGA_ALTERA
|
|
bool "Enable Altera FPGA drivers"
|
|
select FPGA
|
|
help
|
|
Say Y here to enable the Altera FPGA driver
|
|
|
|
This provides basic infrastructure to support Altera FPGA devices.
|
|
Enable Altera FPGA specific functions which includes bitstream
|
|
(in BIT format), fpga and device validation.
|
|
|
|
config FPGA_SOCFPGA
|
|
bool "Enable Gen5 and Arria10 common FPGA drivers"
|
|
select FPGA_ALTERA
|
|
help
|
|
Say Y here to enable the Gen5 and Arria10 common FPGA driver
|
|
|
|
This provides common functionality for Gen5 and Arria10 devices.
|
|
|
|
config FPGA_CYCLON2
|
|
bool "Enable Altera FPGA driver for Cyclone II"
|
|
depends on FPGA_ALTERA
|
|
help
|
|
Say Y here to enable the Altera Cyclone II FPGA specific driver
|
|
|
|
This provides common functionality for Altera Cyclone II devices.
|
|
Enable FPGA driver for loading bitstream in BIT and BIN format
|
|
on Altera Cyclone II device.
|
|
|
|
config FPGA_INTEL_SDM_MAILBOX
|
|
bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
|
|
depends on TARGET_SOCFPGA_SOC64
|
|
select FPGA_ALTERA
|
|
help
|
|
Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
|
|
|
|
This provides common functionality for Intel FPGA devices.
|
|
Enable FPGA driver for writing full bitstream into Intel FPGA
|
|
devices through SDM (Secure Device Manager) Mailbox.
|
|
|
|
config FPGA_XILINX
|
|
bool "Enable Xilinx FPGA drivers"
|
|
select FPGA
|
|
help
|
|
Enable Xilinx FPGA specific functions which includes bitstream
|
|
(in BIT format), fpga and device validation.
|
|
|
|
config FPGA_ZYNQMPPL
|
|
bool "Enable Xilinx FPGA driver for ZynqMP"
|
|
depends on FPGA_XILINX
|
|
help
|
|
Enable FPGA driver for loading bitstream in BIT and BIN format
|
|
on Xilinx Zynq UltraScale+ (ZynqMP) device.
|
|
|
|
config FPGA_VERSALPL
|
|
bool "Enable Xilinx FPGA driver for Versal"
|
|
depends on FPGA_XILINX
|
|
help
|
|
Enable FPGA driver for loading bitstream in PDI format on Xilinx
|
|
Versal device. PDI is a new programmable device image format for
|
|
Versal. The bitstream will only be generated as PDI for Versal
|
|
platform.
|
|
|
|
config FPGA_SPARTAN3
|
|
bool "Enable Spartan3 FPGA driver"
|
|
depends on FPGA_XILINX
|
|
help
|
|
Enable Spartan3 FPGA driver for loading in BIT format.
|
|
|
|
config FPGA_VIRTEX2
|
|
bool "Enable Xilinx Virtex-II and later FPGA driver"
|
|
depends on FPGA_XILINX
|
|
help
|
|
Enable Virtex-II FPGA driver for loading in BIT format. This driver
|
|
also supports many newer Xilinx FPGA families.
|
|
|
|
config FPGA_ZYNQPL
|
|
bool "Enable Xilinx FPGA for Zynq"
|
|
depends on ARCH_ZYNQ
|
|
help
|
|
Enable FPGA driver for loading bitstream in BIT and BIN format
|
|
on Xilinx Zynq devices.
|
|
|
|
endmenu
|