189 lines
5.5 KiB
C
189 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _SDRAM_S10_H_
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#define _SDRAM_S10_H_
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#define DDR_TWR 15
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#define DDR_READ_LATENCY_DELAY 40
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#define DDR_ACTIVATE_FAWBANK 0x1
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/* ECC HMC registers */
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#define DDRIOCTRL 0x8
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#define DDRCALSTAT 0xc
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#define DRAMADDRWIDTH 0xe0
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#define ECCCTRL1 0x100
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#define ECCCTRL2 0x104
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#define ERRINTEN 0x110
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#define ERRINTENS 0x114
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#define INTMODE 0x11c
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#define INTSTAT 0x120
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#define AUTOWB_CORRADDR 0x138
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#define ECC_REG2WRECCDATABUS 0x144
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#define ECC_DIAGON 0x150
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#define ECC_DECSTAT 0x154
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#define HPSINTFCSEL 0x210
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#define RSTHANDSHAKECTRL 0x214
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#define RSTHANDSHAKESTAT 0x218
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#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003
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#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0)
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#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16)
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#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8)
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#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0)
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#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8)
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#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0)
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#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16)
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#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0)
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#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0)
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#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1)
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#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0)
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#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1)
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#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16)
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#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
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#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff
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#define DDR_HMC_CORE2SEQ_INT_REQ 0xF
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#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
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#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
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#define DDR_HMC_ERRINTEN_INTMASK \
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(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \
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DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
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/* NOC DDR scheduler */
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#define DDR_SCH_ID_COREID 0
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#define DDR_SCH_ID_REVID 0x4
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#define DDR_SCH_DDRCONF 0x8
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#define DDR_SCH_DDRTIMING 0xc
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#define DDR_SCH_DDRMODE 0x10
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#define DDR_SCH_READ_LATENCY 0x14
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#define DDR_SCH_ACTIVATE 0x38
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#define DDR_SCH_DEVTODEV 0x3c
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#define DDR_SCH_DDR4TIMING 0x40
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#define DDR_SCH_DDRTIMING_ACTTOACT_OFF 0
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#define DDR_SCH_DDRTIMING_RDTOMISS_OFF 6
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#define DDR_SCH_DDRTIMING_WRTOMISS_OFF 12
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#define DDR_SCH_DDRTIMING_BURSTLEN_OFF 18
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#define DDR_SCH_DDRTIMING_RDTOWR_OFF 21
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#define DDR_SCH_DDRTIMING_WRTORD_OFF 26
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#define DDR_SCH_DDRTIMING_BWRATIO_OFF 31
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#define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF 1
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#define DDR_SCH_ACTIVATE_RRD_OFF 0
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#define DDR_SCH_ACTIVATE_FAW_OFF 4
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#define DDR_SCH_ACTIVATE_FAWBANK_OFF 10
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#define DDR_SCH_DEVTODEV_BUSRDTORD_OFF 0
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#define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2
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#define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4
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/* HMC MMR IO48 registers */
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#define CTRLCFG0 0x28
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#define CTRLCFG1 0x2c
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#define DRAMTIMING0 0x50
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#define CALTIMING0 0x7c
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#define CALTIMING1 0x80
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#define CALTIMING2 0x84
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#define CALTIMING3 0x88
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#define CALTIMING4 0x8c
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#define CALTIMING9 0xa0
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#define DRAMADDRW 0xa8
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#define DRAMSTS 0xec
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#define NIOSRESERVED0 0x110
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#define NIOSRESERVED1 0x114
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#define NIOSRESERVED2 0x118
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#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \
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(((x) >> 0) & 0x1F)
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#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \
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(((x) >> 5) & 0x1F)
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#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \
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(((x) >> 10) & 0xF)
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#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \
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(((x) >> 14) & 0x3)
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#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \
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(((x) >> 16) & 0x7)
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#define CTRLCFG0_CFG_MEMTYPE(x) \
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(((x) >> 0) & 0xF)
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#define CTRLCFG0_CFG_DIMM_TYPE(x) \
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(((x) >> 4) & 0x7)
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#define CTRLCFG0_CFG_AC_POS(x) \
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(((x) >> 7) & 0x3)
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#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \
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(((x) >> 9) & 0x1F)
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#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \
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(((x) >> 0) & 0x1F)
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#define CTRLCFG1_CFG_ADDR_ORDER(x) \
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(((x) >> 5) & 0x3)
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#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \
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(((x) >> 7) & 0x1)
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#define DRAMTIMING0_CFG_TCL(x) \
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(((x) >> 0) & 0x7F)
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#define CALTIMING0_CFG_ACT_TO_RDWR(x) \
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(((x) >> 0) & 0x3F)
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#define CALTIMING0_CFG_ACT_TO_PCH(x) \
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(((x) >> 6) & 0x3F)
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#define CALTIMING0_CFG_ACT_TO_ACT(x) \
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(((x) >> 12) & 0x3F)
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#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \
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(((x) >> 18) & 0x3F)
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#define CALTIMING1_CFG_RD_TO_RD(x) \
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(((x) >> 0) & 0x3F)
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#define CALTIMING1_CFG_RD_TO_RD_DC(x) \
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(((x) >> 6) & 0x3F)
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#define CALTIMING1_CFG_RD_TO_RD_DB(x) \
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(((x) >> 12) & 0x3F)
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#define CALTIMING1_CFG_RD_TO_WR(x) \
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(((x) >> 18) & 0x3F)
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#define CALTIMING1_CFG_RD_TO_WR_DC(x) \
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(((x) >> 24) & 0x3F)
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#define CALTIMING2_CFG_RD_TO_WR_DB(x) \
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(((x) >> 0) & 0x3F)
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#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \
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(((x) >> 6) & 0x3F)
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#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \
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(((x) >> 12) & 0x3F)
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#define CALTIMING2_CFG_WR_TO_WR(x) \
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(((x) >> 18) & 0x3F)
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#define CALTIMING2_CFG_WR_TO_WR_DC(x) \
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(((x) >> 24) & 0x3F)
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#define CALTIMING3_CFG_WR_TO_WR_DB(x) \
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(((x) >> 0) & 0x3F)
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#define CALTIMING3_CFG_WR_TO_RD(x) \
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(((x) >> 6) & 0x3F)
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#define CALTIMING3_CFG_WR_TO_RD_DC(x) \
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(((x) >> 12) & 0x3F)
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#define CALTIMING3_CFG_WR_TO_RD_DB(x) \
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(((x) >> 18) & 0x3F)
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#define CALTIMING3_CFG_WR_TO_PCH(x) \
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(((x) >> 24) & 0x3F)
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#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \
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(((x) >> 0) & 0x3F)
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#define CALTIMING4_CFG_PCH_TO_VALID(x) \
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(((x) >> 6) & 0x3F)
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#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \
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(((x) >> 12) & 0x3F)
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#define CALTIMING4_CFG_ARF_TO_VALID(x) \
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(((x) >> 18) & 0xFF)
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#define CALTIMING4_CFG_PDN_TO_VALID(x) \
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(((x) >> 26) & 0x3F)
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#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
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(((x) >> 0) & 0xFF)
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/* Firewall DDR scheduler MPFE */
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#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
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#define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
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#endif /* _SDRAM_S10_H_ */
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