265 lines
7.0 KiB
C
265 lines
7.0 KiB
C
/*
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include <fsl_ddr.h>
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#include <asm/mmu.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 2,
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.rank_density = 2147483648u,
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.capacity = 4294967296u,
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.primary_sdram_width = 64,
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.ec_sdram_width = 8,
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.registered_dimm = 0,
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.mirrored_dimm = 1,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 2, /* ECC */
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.burst_lengths_bitmask = 0x0c,
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.tckmin_x_ps = 1071,
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.caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
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.taa_ps = 13910,
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.twr_ps = 15000,
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.trcd_ps = 13910,
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.trrd_ps = 6000,
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.trp_ps = 13910,
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.tras_ps = 34000,
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.trc_ps = 48910,
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.trfc_ps = 260000,
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.twtr_ps = 7500,
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.trtp_ps = 7500,
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.refresh_rate_ps = 7800000,
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.tfaw_ps = 35000,
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};
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int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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unsigned int controller_number,
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unsigned int dimm_number)
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{
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const char dimm_model[] = "RAW timing DDR";
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if ((controller_number == 0) && (dimm_number == 0)) {
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memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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}
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return 0;
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}
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2t;
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};
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/*
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* This table contains all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
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* ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
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*/
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{2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
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{2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
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{2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
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{1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
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{1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
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{1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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if (ctrl_num > 2) {
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printf("Not supported controller number %d\n", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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pbsp = udimms[0];
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay =
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pbsp->write_data_delay;
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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popts->twot_en = pbsp->force_2t;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found "
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"for data rate %lu MT/s\n"
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"Trying to use the highest speed (%u) parameters\n",
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ddr_freq, pbsp_highest->datarate_mhz_high);
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popts->cpo_override = pbsp_highest->cpo;
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popts->write_data_delay = pbsp_highest->write_data_delay;
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->wrlvl_start = pbsp_highest->wrlvl_start;
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popts->twot_en = pbsp_highest->force_2t;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/*
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* Rtt and Rtt_WR override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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/* DHC_EN =1, ODT = 75 Ohm */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
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/* optimize cpo for erratum A-009942 */
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popts->cpo_sample = 0x3e;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
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puts("Initializing....using SPD\n");
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fsl_ddr_sdram_size();
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#endif
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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return dram_size;
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}
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unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
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unsigned int dbw_cap_adj[])
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{
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int i, j;
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unsigned long long total_mem, current_mem_base, total_ctlr_mem;
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unsigned long long rank_density, ctlr_density = 0;
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current_mem_base = 0ull;
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total_mem = 0;
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/*
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* This board has soldered DDR chips. DDRC1 has two rank.
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* DDRC2 has only one rank.
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* Assigning DDRC2 to lower address and DDRC1 to higher address.
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*/
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if (pinfo->memctl_opts[0].memctl_interleaving) {
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rank_density = pinfo->dimm_params[0][0].rank_density >>
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dbw_cap_adj[0];
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ctlr_density = rank_density;
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debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
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rank_density, ctlr_density);
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for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
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switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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case FSL_DDR_PAGE_INTERLEAVING:
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case FSL_DDR_BANK_INTERLEAVING:
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case FSL_DDR_SUPERBANK_INTERLEAVING:
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total_ctlr_mem = 2 * ctlr_density;
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break;
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default:
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panic("Unknown interleaving mode");
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}
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pinfo->common_timing_params[i].base_address =
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current_mem_base;
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pinfo->common_timing_params[i].total_mem =
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total_ctlr_mem;
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total_mem = current_mem_base + total_ctlr_mem;
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debug("ctrl %d base 0x%llx\n", i, current_mem_base);
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debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
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}
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} else {
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/*
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* Simple linear assignment if memory
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* controllers are not interleaved.
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*/
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for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
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total_ctlr_mem = 0;
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pinfo->common_timing_params[i].base_address =
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current_mem_base;
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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/* Compute DIMM base addresses. */
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unsigned long long cap =
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pinfo->dimm_params[i][j].capacity;
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pinfo->dimm_params[i][j].base_address =
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current_mem_base;
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debug("ctrl %d dimm %d base 0x%llx\n",
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i, j, current_mem_base);
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current_mem_base += cap;
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total_ctlr_mem += cap;
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}
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debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
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pinfo->common_timing_params[i].total_mem =
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total_ctlr_mem;
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total_mem += total_ctlr_mem;
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}
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}
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debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
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return total_mem;
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}
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