144 lines
3.6 KiB
C
144 lines
3.6 KiB
C
/*
|
|
* Copyright 2016 Freescale Semiconductor, Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <fsl_ddr_sdram.h>
|
|
#include <fsl_ddr_dimm_params.h>
|
|
#ifdef CONFIG_FSL_DEEP_SLEEP
|
|
#include <fsl_sleep.h>
|
|
#endif
|
|
#include "ddr.h"
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
void fsl_ddr_board_options(memctl_options_t *popts,
|
|
dimm_params_t *pdimm,
|
|
unsigned int ctrl_num)
|
|
{
|
|
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
|
|
ulong ddr_freq;
|
|
|
|
if (ctrl_num > 3) {
|
|
printf("Not supported controller number %d\n", ctrl_num);
|
|
return;
|
|
}
|
|
if (!pdimm->n_ranks)
|
|
return;
|
|
|
|
pbsp = udimms[0];
|
|
|
|
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
|
|
* freqency and n_banks specified in board_specific_parameters table.
|
|
*/
|
|
ddr_freq = get_ddr_freq(0) / 1000000;
|
|
while (pbsp->datarate_mhz_high) {
|
|
if (pbsp->n_ranks == pdimm->n_ranks) {
|
|
if (ddr_freq <= pbsp->datarate_mhz_high) {
|
|
popts->clk_adjust = pbsp->clk_adjust;
|
|
popts->wrlvl_start = pbsp->wrlvl_start;
|
|
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
|
|
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
|
|
goto found;
|
|
}
|
|
pbsp_highest = pbsp;
|
|
}
|
|
pbsp++;
|
|
}
|
|
|
|
if (pbsp_highest) {
|
|
printf("Error: board specific timing not found for %lu MT/s\n",
|
|
ddr_freq);
|
|
printf("Trying to use the highest speed (%u) parameters\n",
|
|
pbsp_highest->datarate_mhz_high);
|
|
popts->clk_adjust = pbsp_highest->clk_adjust;
|
|
popts->wrlvl_start = pbsp_highest->wrlvl_start;
|
|
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
|
|
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
|
|
} else {
|
|
panic("DIMM is not supported by this board");
|
|
}
|
|
found:
|
|
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
|
|
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
|
|
|
|
popts->data_bus_width = 0; /* 64b data bus */
|
|
popts->otf_burst_chop_en = 0;
|
|
popts->burst_length = DDR_BL8;
|
|
popts->bstopre = 0; /* enable auto precharge */
|
|
|
|
popts->half_strength_driver_enable = 0;
|
|
/*
|
|
* Write leveling override
|
|
*/
|
|
popts->wrlvl_override = 1;
|
|
popts->wrlvl_sample = 0xf;
|
|
|
|
/*
|
|
* Rtt and Rtt_WR override
|
|
*/
|
|
popts->rtt_override = 0;
|
|
|
|
/* Enable ZQ calibration */
|
|
popts->zq_en = 1;
|
|
|
|
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
|
|
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
|
|
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
|
|
|
|
/* optimize cpo for erratum A-009942 */
|
|
popts->cpo_sample = 0x70;
|
|
}
|
|
|
|
phys_size_t initdram(int board_type)
|
|
{
|
|
phys_size_t dram_size;
|
|
|
|
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
|
|
return fsl_ddr_sdram_size();
|
|
#else
|
|
puts("Initializing DDR....using SPD\n");
|
|
|
|
dram_size = fsl_ddr_sdram();
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_DEEP_SLEEP
|
|
fsl_dp_ddr_restore();
|
|
#endif
|
|
|
|
erratum_a008850_post();
|
|
|
|
return dram_size;
|
|
}
|
|
|
|
void dram_init_banksize(void)
|
|
{
|
|
/*
|
|
* gd->arch.secure_ram tracks the location of secure memory.
|
|
* It was set as if the memory starts from 0.
|
|
* The address needs to add the offset of its bank.
|
|
*/
|
|
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
|
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
|
|
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
|
|
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
|
|
gd->bd->bi_dram[1].size = gd->ram_size -
|
|
CONFIG_SYS_DDR_BLOCK1_SIZE;
|
|
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
|
gd->arch.secure_ram = gd->bd->bi_dram[1].start +
|
|
gd->arch.secure_ram -
|
|
CONFIG_SYS_DDR_BLOCK1_SIZE;
|
|
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
|
|
#endif
|
|
} else {
|
|
gd->bd->bi_dram[0].size = gd->ram_size;
|
|
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
|
|
gd->arch.secure_ram = gd->bd->bi_dram[0].start +
|
|
gd->arch.secure_ram;
|
|
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
|
|
#endif
|
|
}
|
|
}
|