769 lines
18 KiB
C
769 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* Based on code from coreboot src/soc/intel/broadwell/cpu.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <cpu.h>
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#include <asm/cpu.h>
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#include <asm/cpu_x86.h>
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#include <asm/cpu_common.h>
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#include <asm/intel_regs.h>
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#include <asm/msr.h>
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#include <asm/post.h>
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#include <asm/turbo.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/rcb.h>
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struct cpu_broadwell_priv {
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bool ht_disabled;
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};
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/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
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static const u8 power_limit_time_sec_to_msr[] = {
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[0] = 0x00,
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[1] = 0x0a,
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[2] = 0x0b,
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[3] = 0x4b,
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[4] = 0x0c,
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[5] = 0x2c,
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[6] = 0x4c,
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[7] = 0x6c,
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[8] = 0x0d,
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[10] = 0x2d,
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[12] = 0x4d,
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[14] = 0x6d,
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[16] = 0x0e,
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[20] = 0x2e,
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[24] = 0x4e,
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[28] = 0x6e,
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[32] = 0x0f,
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[40] = 0x2f,
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[48] = 0x4f,
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[56] = 0x6f,
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[64] = 0x10,
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[80] = 0x30,
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[96] = 0x50,
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[112] = 0x70,
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[128] = 0x11,
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};
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/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
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static const u8 power_limit_time_msr_to_sec[] = {
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[0x00] = 0,
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[0x0a] = 1,
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[0x0b] = 2,
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[0x4b] = 3,
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[0x0c] = 4,
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[0x2c] = 5,
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[0x4c] = 6,
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[0x6c] = 7,
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[0x0d] = 8,
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[0x2d] = 10,
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[0x4d] = 12,
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[0x6d] = 14,
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[0x0e] = 16,
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[0x2e] = 20,
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[0x4e] = 24,
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[0x6e] = 28,
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[0x0f] = 32,
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[0x2f] = 40,
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[0x4f] = 48,
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[0x6f] = 56,
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[0x10] = 64,
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[0x30] = 80,
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[0x50] = 96,
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[0x70] = 112,
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[0x11] = 128,
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};
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int arch_cpu_init_dm(void)
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{
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struct udevice *dev;
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int ret;
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/* Start up the LPC so we have serial */
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ret = uclass_first_device(UCLASS_LPC, &dev);
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if (ret)
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return ret;
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if (!dev)
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return -ENODEV;
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ret = cpu_set_flex_ratio_to_tdp_nominal();
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if (ret)
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return ret;
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return 0;
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}
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void set_max_freq(void)
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{
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msr_t msr, perf_ctl, platform_info;
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/* Check for configurable TDP option */
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platform_info = msr_read(MSR_PLATFORM_INFO);
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if ((platform_info.hi >> 1) & 3) {
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/* Set to nominal TDP ratio */
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msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
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perf_ctl.lo = (msr.lo & 0xff) << 8;
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} else {
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/* Platform Info bits 15:8 give max ratio */
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msr = msr_read(MSR_PLATFORM_INFO);
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perf_ctl.lo = msr.lo & 0xff00;
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}
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perf_ctl.hi = 0;
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msr_write(IA32_PERF_CTL, perf_ctl);
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debug("CPU: frequency set to %d MHz\n",
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((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
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}
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int arch_cpu_init(void)
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{
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post_code(POST_CPU_INIT);
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return x86_cpu_init_f();
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}
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int checkcpu(void)
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{
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int ret;
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set_max_freq();
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ret = cpu_common_init();
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if (ret)
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return ret;
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gd->arch.pei_boot_mode = PEI_BOOT_NONE;
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return 0;
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}
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int print_cpuinfo(void)
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{
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char processor_name[CPU_MAX_NAME_LEN];
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const char *name;
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/* Print processor name */
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name = cpu_get_name(processor_name);
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printf("CPU: %s\n", name);
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return 0;
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}
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/*
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* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
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* the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
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* when a core is woken up
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*/
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static int pcode_ready(void)
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{
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int wait_count;
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const int delay_step = 10;
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wait_count = 0;
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do {
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if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
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MAILBOX_RUN_BUSY))
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return 0;
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wait_count += delay_step;
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udelay(delay_step);
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} while (wait_count < 1000);
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return -ETIMEDOUT;
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}
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static u32 pcode_mailbox_read(u32 command)
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{
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int ret;
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ret = pcode_ready();
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if (ret) {
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debug("PCODE: mailbox timeout on wait ready\n");
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return ret;
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}
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/* Send command and start transaction */
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writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
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ret = pcode_ready();
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if (ret) {
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debug("PCODE: mailbox timeout on completion\n");
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return ret;
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}
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/* Read mailbox */
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return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
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}
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static int pcode_mailbox_write(u32 command, u32 data)
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{
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int ret;
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ret = pcode_ready();
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if (ret) {
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debug("PCODE: mailbox timeout on wait ready\n");
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return ret;
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}
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writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
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/* Send command and start transaction */
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writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
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ret = pcode_ready();
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if (ret) {
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debug("PCODE: mailbox timeout on completion\n");
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return ret;
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}
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return 0;
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}
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/* @dev is the CPU device */
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static void initialize_vr_config(struct udevice *dev)
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{
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int ramp, min_vid;
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msr_t msr;
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debug("Initializing VR config\n");
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/* Configure VR_CURRENT_CONFIG */
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msr = msr_read(MSR_VR_CURRENT_CONFIG);
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/*
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* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
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* on ULT systems
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*/
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msr.hi &= 0xc0000000;
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msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */
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msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */
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msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
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msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
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/* Leave the max instantaneous current limit (12:0) to default */
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msr_write(MSR_VR_CURRENT_CONFIG, msr);
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/* Configure VR_MISC_CONFIG MSR */
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msr = msr_read(MSR_VR_MISC_CONFIG);
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/* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
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msr.hi &= ~(0x3ff << (40 - 32));
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msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
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/* Set IOUT_OFFSET to 0 */
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msr.hi &= ~0xff;
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/* Set entry ramp rate to slow */
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msr.hi &= ~(1 << (51 - 32));
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/* Enable decay mode on C-state entry */
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msr.hi |= (1 << (52 - 32));
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/* Set the slow ramp rate */
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msr.hi &= ~(0x3 << (53 - 32));
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/* Configure the C-state exit ramp rate */
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ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"intel,slow-ramp", -1);
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if (ramp != -1) {
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/* Configured slow ramp rate */
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msr.hi |= ((ramp & 0x3) << (53 - 32));
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/* Set exit ramp rate to slow */
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msr.hi &= ~(1 << (50 - 32));
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} else {
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/* Fast ramp rate / 4 */
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msr.hi |= (0x01 << (53 - 32));
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/* Set exit ramp rate to fast */
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msr.hi |= (1 << (50 - 32));
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}
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/* Set MIN_VID (31:24) to allow CPU to have full control */
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msr.lo &= ~0xff000000;
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min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"intel,min-vid", 0);
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msr.lo |= (min_vid & 0xff) << 24;
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msr_write(MSR_VR_MISC_CONFIG, msr);
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/* Configure VR_MISC_CONFIG2 MSR */
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msr = msr_read(MSR_VR_MISC_CONFIG2);
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msr.lo &= ~0xffff;
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/*
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* Allow CPU to control minimum voltage completely (15:8) and
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* set the fast ramp voltage in 10mV steps
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*/
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if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
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msr.lo |= 0x006a; /* 1.56V */
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else
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msr.lo |= 0x006f; /* 1.60V */
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msr_write(MSR_VR_MISC_CONFIG2, msr);
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/* Set C9/C10 VCC Min */
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pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
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}
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static int calibrate_24mhz_bclk(void)
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{
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int err_code;
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int ret;
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ret = pcode_ready();
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if (ret)
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return ret;
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/* A non-zero value initiates the PCODE calibration */
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writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
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writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
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MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
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ret = pcode_ready();
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if (ret)
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return ret;
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err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
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debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
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/* Read the calibrated value */
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writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
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MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
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ret = pcode_ready();
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if (ret)
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return ret;
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debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
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readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
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return 0;
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}
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static void configure_pch_power_sharing(void)
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{
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u32 pch_power, pch_power_ext, pmsync, pmsync2;
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int i;
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/* Read PCH Power levels from PCODE */
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pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
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pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
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debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
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pch_power_ext);
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pmsync = readl(RCB_REG(PMSYNC_CONFIG));
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pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
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/*
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* Program PMSYNC_TPR_CONFIG PCH power limit values
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* pmsync[0:4] = mailbox[0:5]
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* pmsync[8:12] = mailbox[6:11]
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* pmsync[16:20] = mailbox[12:17]
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*/
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for (i = 0; i < 3; i++) {
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u32 level = pch_power & 0x3f;
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pch_power >>= 6;
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pmsync &= ~(0x1f << (i * 8));
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pmsync |= (level & 0x1f) << (i * 8);
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}
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writel(pmsync, RCB_REG(PMSYNC_CONFIG));
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/*
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* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
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* pmsync2[0:4] = mailbox[23:18]
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* pmsync2[8:12] = mailbox_ext[6:11]
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* pmsync2[16:20] = mailbox_ext[12:17]
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* pmsync2[24:28] = mailbox_ext[18:22]
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*/
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pmsync2 &= ~0x1f;
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pmsync2 |= pch_power & 0x1f;
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for (i = 1; i < 4; i++) {
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u32 level = pch_power_ext & 0x3f;
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pch_power_ext >>= 6;
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pmsync2 &= ~(0x1f << (i * 8));
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pmsync2 |= (level & 0x1f) << (i * 8);
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}
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writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
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}
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static int bsp_init_before_ap_bringup(struct udevice *dev)
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{
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int ret;
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initialize_vr_config(dev);
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ret = calibrate_24mhz_bclk();
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if (ret)
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return ret;
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configure_pch_power_sharing();
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return 0;
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}
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int cpu_config_tdp_levels(void)
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{
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msr_t platform_info;
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/* Bits 34:33 indicate how many levels supported */
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platform_info = msr_read(MSR_PLATFORM_INFO);
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return (platform_info.hi >> 1) & 3;
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}
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static void set_max_ratio(void)
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{
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msr_t msr, perf_ctl;
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perf_ctl.hi = 0;
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/* Check for configurable TDP option */
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if (turbo_get_state() == TURBO_ENABLED) {
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msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT);
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perf_ctl.lo = (msr.lo & 0xff) << 8;
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} else if (cpu_config_tdp_levels()) {
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/* Set to nominal TDP ratio */
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msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
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perf_ctl.lo = (msr.lo & 0xff) << 8;
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} else {
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/* Platform Info bits 15:8 give max ratio */
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msr = msr_read(MSR_PLATFORM_INFO);
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perf_ctl.lo = msr.lo & 0xff00;
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}
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msr_write(IA32_PERF_CTL, perf_ctl);
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debug("cpu: frequency set to %d\n",
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((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
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}
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int broadwell_init(struct udevice *dev)
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{
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struct cpu_broadwell_priv *priv = dev_get_priv(dev);
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int num_threads;
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int num_cores;
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msr_t msr;
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int ret;
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msr = msr_read(CORE_THREAD_COUNT_MSR);
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num_threads = (msr.lo >> 0) & 0xffff;
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num_cores = (msr.lo >> 16) & 0xffff;
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debug("CPU has %u cores, %u threads enabled\n", num_cores,
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num_threads);
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priv->ht_disabled = num_threads == num_cores;
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ret = bsp_init_before_ap_bringup(dev);
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if (ret)
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return ret;
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set_max_ratio();
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return ret;
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}
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static void configure_mca(void)
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{
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msr_t msr;
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const unsigned int mcg_cap_msr = 0x179;
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int i;
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int num_banks;
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msr = msr_read(mcg_cap_msr);
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num_banks = msr.lo & 0xff;
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msr.lo = 0;
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msr.hi = 0;
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/*
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* TODO(adurbin): This should only be done on a cold boot. Also, some
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* of these banks are core vs package scope. For now every CPU clears
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* every bank
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*/
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for (i = 0; i < num_banks; i++)
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msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
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}
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static void enable_lapic_tpr(void)
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{
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msr_t msr;
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msr = msr_read(MSR_PIC_MSG_CONTROL);
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msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
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msr_write(MSR_PIC_MSG_CONTROL, msr);
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}
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static void configure_c_states(void)
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{
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msr_t msr;
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msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
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msr.lo |= (1 << 31); /* Timed MWAIT Enable */
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msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */
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msr.lo |= (1 << 29); /* Package c-state Demotion Enable */
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msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
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msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
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msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
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msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
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msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
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/* The deepest package c-state defaults to factory-configured value */
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|
msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
|
|
|
|
msr = msr_read(MSR_MISC_PWR_MGMT);
|
|
msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
|
|
msr_write(MSR_MISC_PWR_MGMT, msr);
|
|
|
|
msr = msr_read(MSR_POWER_CTL);
|
|
msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
|
|
msr.lo |= (1 << 1); /* C1E Enable */
|
|
msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
|
|
msr_write(MSR_POWER_CTL, msr);
|
|
|
|
/* C-state Interrupt Response Latency Control 0 - package C3 latency */
|
|
msr.hi = 0;
|
|
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
|
|
msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
|
|
|
|
/* C-state Interrupt Response Latency Control 1 */
|
|
msr.hi = 0;
|
|
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
|
|
msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
|
|
|
|
/* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
|
|
msr.hi = 0;
|
|
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
|
|
msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
|
|
|
|
/* C-state Interrupt Response Latency Control 3 - package C8 */
|
|
msr.hi = 0;
|
|
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
|
|
msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
|
|
|
|
/* C-state Interrupt Response Latency Control 4 - package C9 */
|
|
msr.hi = 0;
|
|
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
|
|
msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
|
|
|
|
/* C-state Interrupt Response Latency Control 5 - package C10 */
|
|
msr.hi = 0;
|
|
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
|
|
msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
|
|
}
|
|
|
|
static void configure_misc(void)
|
|
{
|
|
msr_t msr;
|
|
|
|
msr = msr_read(MSR_IA32_MISC_ENABLE);
|
|
msr.lo |= (1 << 0); /* Fast String enable */
|
|
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
|
|
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
|
|
msr_write(MSR_IA32_MISC_ENABLE, msr);
|
|
|
|
/* Disable thermal interrupts */
|
|
msr.lo = 0;
|
|
msr.hi = 0;
|
|
msr_write(MSR_IA32_THERM_INTERRUPT, msr);
|
|
|
|
/* Enable package critical interrupt only */
|
|
msr.lo = 1 << 4;
|
|
msr.hi = 0;
|
|
msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
|
|
}
|
|
|
|
static void configure_thermal_target(struct udevice *dev)
|
|
{
|
|
int tcc_offset;
|
|
msr_t msr;
|
|
|
|
tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
|
|
"intel,tcc-offset", 0);
|
|
|
|
/* Set TCC activaiton offset if supported */
|
|
msr = msr_read(MSR_PLATFORM_INFO);
|
|
if ((msr.lo & (1 << 30)) && tcc_offset) {
|
|
msr = msr_read(MSR_TEMPERATURE_TARGET);
|
|
msr.lo &= ~(0xf << 24); /* Bits 27:24 */
|
|
msr.lo |= (tcc_offset & 0xf) << 24;
|
|
msr_write(MSR_TEMPERATURE_TARGET, msr);
|
|
}
|
|
}
|
|
|
|
static void configure_dca_cap(void)
|
|
{
|
|
struct cpuid_result cpuid_regs;
|
|
msr_t msr;
|
|
|
|
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
|
|
cpuid_regs = cpuid(1);
|
|
if (cpuid_regs.ecx & (1 << 18)) {
|
|
msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
|
|
msr.lo |= 1;
|
|
msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
|
|
}
|
|
}
|
|
|
|
static void set_energy_perf_bias(u8 policy)
|
|
{
|
|
msr_t msr;
|
|
int ecx;
|
|
|
|
/* Determine if energy efficient policy is supported */
|
|
ecx = cpuid_ecx(0x6);
|
|
if (!(ecx & (1 << 3)))
|
|
return;
|
|
|
|
/* Energy Policy is bits 3:0 */
|
|
msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
|
|
msr.lo &= ~0xf;
|
|
msr.lo |= policy & 0xf;
|
|
msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
|
|
|
|
debug("cpu: energy policy set to %u\n", policy);
|
|
}
|
|
|
|
/* All CPUs including BSP will run the following function */
|
|
static void cpu_core_init(struct udevice *dev)
|
|
{
|
|
/* Clear out pending MCEs */
|
|
configure_mca();
|
|
|
|
/* Enable the local cpu apics */
|
|
enable_lapic_tpr();
|
|
|
|
/* Configure C States */
|
|
configure_c_states();
|
|
|
|
/* Configure Enhanced SpeedStep and Thermal Sensors */
|
|
configure_misc();
|
|
|
|
/* Thermal throttle activation offset */
|
|
configure_thermal_target(dev);
|
|
|
|
/* Enable Direct Cache Access */
|
|
configure_dca_cap();
|
|
|
|
/* Set energy policy */
|
|
set_energy_perf_bias(ENERGY_POLICY_NORMAL);
|
|
|
|
/* Enable Turbo */
|
|
turbo_enable();
|
|
}
|
|
|
|
/*
|
|
* Configure processor power limits if possible
|
|
* This must be done AFTER set of BIOS_RESET_CPL
|
|
*/
|
|
void cpu_set_power_limits(int power_limit_1_time)
|
|
{
|
|
msr_t msr;
|
|
msr_t limit;
|
|
unsigned power_unit;
|
|
unsigned tdp, min_power, max_power, max_time;
|
|
u8 power_limit_1_val;
|
|
|
|
msr = msr_read(MSR_PLATFORM_INFO);
|
|
if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
|
|
power_limit_1_time = 28;
|
|
|
|
if (!(msr.lo & PLATFORM_INFO_SET_TDP))
|
|
return;
|
|
|
|
/* Get units */
|
|
msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
|
|
power_unit = 2 << ((msr.lo & 0xf) - 1);
|
|
|
|
/* Get power defaults for this SKU */
|
|
msr = msr_read(MSR_PKG_POWER_SKU);
|
|
tdp = msr.lo & 0x7fff;
|
|
min_power = (msr.lo >> 16) & 0x7fff;
|
|
max_power = msr.hi & 0x7fff;
|
|
max_time = (msr.hi >> 16) & 0x7f;
|
|
|
|
debug("CPU TDP: %u Watts\n", tdp / power_unit);
|
|
|
|
if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
|
|
power_limit_1_time = power_limit_time_msr_to_sec[max_time];
|
|
|
|
if (min_power > 0 && tdp < min_power)
|
|
tdp = min_power;
|
|
|
|
if (max_power > 0 && tdp > max_power)
|
|
tdp = max_power;
|
|
|
|
power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
|
|
|
|
/* Set long term power limit to TDP */
|
|
limit.lo = 0;
|
|
limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
|
|
limit.lo |= PKG_POWER_LIMIT_EN;
|
|
limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
|
|
PKG_POWER_LIMIT_TIME_SHIFT;
|
|
|
|
/* Set short term power limit to 1.25 * TDP */
|
|
limit.hi = 0;
|
|
limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
|
|
limit.hi |= PKG_POWER_LIMIT_EN;
|
|
/* Power limit 2 time is only programmable on server SKU */
|
|
|
|
msr_write(MSR_PKG_POWER_LIMIT, limit);
|
|
|
|
/* Set power limit values in MCHBAR as well */
|
|
writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
|
|
writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
|
|
|
|
/* Set DDR RAPL power limit by copying from MMIO to MSR */
|
|
msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
|
|
msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
|
|
msr_write(MSR_DDR_RAPL_LIMIT, msr);
|
|
|
|
/* Use nominal TDP values for CPUs with configurable TDP */
|
|
if (cpu_config_tdp_levels()) {
|
|
msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
|
|
limit.hi = 0;
|
|
limit.lo = msr.lo & 0xff;
|
|
msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
|
|
}
|
|
}
|
|
|
|
static int broadwell_get_info(struct udevice *dev, struct cpu_info *info)
|
|
{
|
|
msr_t msr;
|
|
|
|
msr = msr_read(IA32_PERF_CTL);
|
|
info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000;
|
|
info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
|
|
1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int broadwell_get_count(struct udevice *dev)
|
|
{
|
|
return 4;
|
|
}
|
|
|
|
static int cpu_x86_broadwell_probe(struct udevice *dev)
|
|
{
|
|
if (dev->seq == 0) {
|
|
cpu_core_init(dev);
|
|
return broadwell_init(dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct cpu_ops cpu_x86_broadwell_ops = {
|
|
.get_desc = cpu_x86_get_desc,
|
|
.get_info = broadwell_get_info,
|
|
.get_count = broadwell_get_count,
|
|
.get_vendor = cpu_x86_get_vendor,
|
|
};
|
|
|
|
static const struct udevice_id cpu_x86_broadwell_ids[] = {
|
|
{ .compatible = "intel,core-i3-gen5" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
|
|
.name = "cpu_x86_broadwell",
|
|
.id = UCLASS_CPU,
|
|
.of_match = cpu_x86_broadwell_ids,
|
|
.bind = cpu_x86_bind,
|
|
.probe = cpu_x86_broadwell_probe,
|
|
.ops = &cpu_x86_broadwell_ops,
|
|
.priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv),
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
};
|