49 lines
1.4 KiB
C
49 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Keystone2: DDR3 configuration
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#include <common.h>
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#include <asm/arch/ddr3.h>
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#include "ddr3_cfg.h"
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struct ddr3_phy_config ddr3phy_1600_2g = {
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.pllcr = 0x0001C000ul,
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.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
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.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
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.ptr0 = 0x42C21590ul,
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.ptr1 = 0xD05612C0ul,
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.ptr2 = 0, /* not set in gel */
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.ptr3 = 0x0D861A80ul,
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.ptr4 = 0x0C827100ul,
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.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
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.dcr_val = ((1 << 10)),
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.dtpr0 = 0x9D5CBB66ul,
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.dtpr1 = 0x12868300ul,
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.dtpr2 = 0x5002D200ul,
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.mr0 = 0x00001C70ul,
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.mr1 = 0x00000006ul,
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.mr2 = 0x00000018ul,
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.dtcr = 0x710035C7ul,
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.pgcr2 = 0x00F07A12ul,
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.zq0cr1 = 0x0001005Dul,
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.zq1cr1 = 0x0001005Bul,
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.zq2cr1 = 0x0001005Bul,
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.pir_v1 = 0x00000033ul,
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.pir_v2 = 0x0000FF81ul,
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};
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struct ddr3_emif_config ddr3_1600_2g = {
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.sdcfg = 0x6200CE62ul,
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.sdtim1 = 0x166C9855ul,
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.sdtim2 = 0x00001D4Aul,
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.sdtim3 = 0x435DFF53ul,
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.sdtim4 = 0x543F0CFFul,
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.zqcfg = 0x70073200ul,
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.sdrfc = 0x00001869ul,
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};
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