168 lines
6.0 KiB
C
168 lines
6.0 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* Referred to Linux Kernel DSS driver files for OMAP3 by
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* Tomi Valkeinen from drivers/video/omap2/dss/
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation's version 2 and any
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* later version the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/dss.h>
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#include <video_fb.h>
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/* Configure VENC for a given Mode (NTSC / PAL) */
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void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
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u32 height, u32 width)
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{
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struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE;
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struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
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struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
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writel(venc_cfg->status, &venc->status);
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writel(venc_cfg->f_control, &venc->f_control);
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writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl);
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writel(venc_cfg->sync_ctrl, &venc->sync_ctrl);
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writel(venc_cfg->llen, &venc->llen);
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writel(venc_cfg->flens, &venc->flens);
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writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl);
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writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr);
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writel(venc_cfg->c_phase, &venc->c_phase);
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writel(venc_cfg->gain_u, &venc->gain_u);
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writel(venc_cfg->gain_v, &venc->gain_v);
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writel(venc_cfg->gain_y, &venc->gain_y);
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writel(venc_cfg->black_level, &venc->black_level);
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writel(venc_cfg->blank_level, &venc->blank_level);
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writel(venc_cfg->x_color, &venc->x_color);
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writel(venc_cfg->m_control, &venc->m_control);
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writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data);
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writel(venc_cfg->s_carr, &venc->s_carr);
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writel(venc_cfg->line21, &venc->line21);
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writel(venc_cfg->ln_sel, &venc->ln_sel);
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writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl);
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writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger);
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writel(venc_cfg->savid__eavid, &venc->savid__eavid);
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writel(venc_cfg->flen__fal, &venc->flen__fal);
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writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
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writel(venc_cfg->hs_int_start_stop_x, &venc->hs_int_start_stop_x);
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writel(venc_cfg->hs_ext_start_stop_x, &venc->hs_ext_start_stop_x);
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writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
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writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
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&venc->vs_int_stop_x__vs_int_start_y);
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writel(venc_cfg->vs_int_stop_y__vs_ext_start_x,
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&venc->vs_int_stop_y__vs_ext_start_x);
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writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y,
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&venc->vs_ext_stop_x__vs_ext_start_y);
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writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y);
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writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x);
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writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y);
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writel(venc_cfg->fid_int_start_x__fid_int_start_y,
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&venc->fid_int_start_x__fid_int_start_y);
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writel(venc_cfg->fid_int_offset_y__fid_ext_start_x,
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&venc->fid_int_offset_y__fid_ext_start_x);
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writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y,
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&venc->fid_ext_start_y__fid_ext_offset_y);
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writel(venc_cfg->tvdetgp_int_start_stop_x,
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&venc->tvdetgp_int_start_stop_x);
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writel(venc_cfg->tvdetgp_int_start_stop_y,
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&venc->tvdetgp_int_start_stop_y);
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writel(venc_cfg->gen_ctrl, &venc->gen_ctrl);
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writel(venc_cfg->output_control, &venc->output_control);
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writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);
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/* Configure DSS for VENC Settings */
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writel(VENC_CLK_ENABLE | DAC_DEMEN | DAC_POWERDN | VENC_OUT_SEL,
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&dss->control);
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/* Configure height and width for Digital out */
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writel(height << DIG_LPP_SHIFT | width, &dispc->size_dig);
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}
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/* Configure Panel Specific Parameters */
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void omap3_dss_panel_config(const struct panel_config *panel_cfg)
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{
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struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
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struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
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writel(DSS_SOFTRESET, &dss->sysconfig);
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while (!(readl(&dss->sysstatus) & DSS_RESETDONE))
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;
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writel(panel_cfg->timing_h, &dispc->timing_h);
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writel(panel_cfg->timing_v, &dispc->timing_v);
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writel(panel_cfg->pol_freq, &dispc->pol_freq);
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writel(panel_cfg->divisor, &dispc->divisor);
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writel(panel_cfg->lcd_size, &dispc->size_lcd);
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writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config);
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writel(panel_cfg->panel_type << TFTSTN_SHIFT |
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panel_cfg->data_lines << DATALINES_SHIFT, &dispc->control);
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writel(panel_cfg->panel_color, &dispc->default_color0);
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writel((u32) panel_cfg->frame_buffer, &dispc->gfx_ba0);
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if (!panel_cfg->frame_buffer)
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return;
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writel(panel_cfg->gfx_format | GFX_ENABLE, &dispc->gfx_attributes);
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writel(1, &dispc->gfx_row_inc);
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writel(1, &dispc->gfx_pixel_inc);
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writel(panel_cfg->lcd_size, &dispc->gfx_size);
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}
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/* Enable LCD and DIGITAL OUT in DSS */
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void omap3_dss_enable(void)
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{
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struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
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u32 l;
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l = readl(&dispc->control);
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l |= LCD_ENABLE | GO_LCD | DIG_ENABLE | GO_DIG | GP_OUT0 | GP_OUT1;
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writel(l, &dispc->control);
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}
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#ifdef CONFIG_CFB_CONSOLE
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int __board_video_init(void)
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{
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return -1;
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}
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int board_video_init(void)
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__attribute__((weak, alias("__board_video_init")));
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void *video_hw_init(void)
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{
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static GraphicDevice dssfb;
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GraphicDevice *pGD = &dssfb;
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struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
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if (board_video_init() || !readl(&dispc->gfx_ba0))
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return NULL;
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pGD->winSizeX = (readl(&dispc->size_lcd) & 0x7FF) + 1;
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pGD->winSizeY = ((readl(&dispc->size_lcd) >> 16) & 0x7FF) + 1;
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pGD->gdfBytesPP = 4;
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pGD->gdfIndex = GDF_32BIT_X888RGB;
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pGD->frameAdrs = readl(&dispc->gfx_ba0);
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return pGD;
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}
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#endif
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