84 lines
1.7 KiB
C
84 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*
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* U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
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* The CLINT block holds memory-mapped control and status registers
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* associated with software and timer interrupts.
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*/
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#include <common.h>
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#include <dm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/syscon.h>
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#include <linux/err.h>
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/* MSIP registers */
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#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
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/* mtime compare register */
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#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8)
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/* mtime register */
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#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
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DECLARE_GLOBAL_DATA_PTR;
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int riscv_get_time(u64 *time)
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{
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*time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
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return 0;
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}
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int riscv_set_timecmp(int hart, u64 cmp)
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{
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writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
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return 0;
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}
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int riscv_init_ipi(void)
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{
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long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
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if (IS_ERR(ret))
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return PTR_ERR(ret);
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gd->arch.clint = ret;
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return 0;
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}
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int riscv_send_ipi(int hart)
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{
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writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
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return 0;
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}
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int riscv_clear_ipi(int hart)
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{
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writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
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return 0;
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}
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int riscv_get_ipi(int hart, int *pending)
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{
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*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
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return 0;
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}
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static const struct udevice_id sifive_clint_ids[] = {
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{ .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
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{ }
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};
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U_BOOT_DRIVER(sifive_clint) = {
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.name = "sifive_clint",
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.id = UCLASS_SYSCON,
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.of_match = sifive_clint_ids,
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.flags = DM_FLAG_PRE_RELOC,
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};
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