263 lines
6.2 KiB
C
263 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015 Savoir-faire Linux Inc.
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*
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* Derived from MX51EVK code by
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* Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <init.h>
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#include <log.h>
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#include <net.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx51.h>
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#include <env.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/mx5_video.h>
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#include <mmc.h>
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#include <input.h>
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#include <fsl_esdhc_imx.h>
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#include <mc13892.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <phy.h>
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#include "ts4800.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_FSL_ESDHC_IMX
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR},
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{MMC_SDHC2_BASE_ADDR},
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};
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#endif
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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u32 get_board_rev(void)
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{
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u32 rev = get_cpu_rev();
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if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
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rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
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return rev;
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}
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#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
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static void setup_iomux_uart(void)
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{
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static const iomux_v3_cfg_t uart_pads[] = {
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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static void setup_iomux_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO,
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PAD_CTL_HYS |
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PAD_CTL_PUS_22K_UP |
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
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MX51_PAD_EIM_EB3__FEC_RDATA1,
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NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS),
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MX51_PAD_EIM_CS3__FEC_RDATA3,
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MX51_PAD_NANDF_CS2__FEC_TX_ER,
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MX51_PAD_EIM_CS5__FEC_CRS,
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MX51_PAD_EIM_CS4__FEC_RX_ER,
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/* PAD used on TS4800 */
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MX51_PAD_DI2_PIN2__FEC_MDC,
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MX51_PAD_DISP2_DAT14__FEC_RDAT0,
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MX51_PAD_DISP2_DAT10__FEC_COL,
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MX51_PAD_DISP2_DAT11__FEC_RXCLK,
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MX51_PAD_DISP2_DAT15__FEC_TDAT0,
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MX51_PAD_DISP2_DAT6__FEC_TDAT1,
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MX51_PAD_DISP2_DAT7__FEC_TDAT2,
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MX51_PAD_DISP2_DAT8__FEC_TDAT3,
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MX51_PAD_DISP2_DAT9__FEC_TX_EN,
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MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
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MX51_PAD_DISP2_DAT12__FEC_RX_DV,
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};
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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#ifdef CONFIG_FSL_ESDHC_IMX
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret;
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
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NO_PAD_CTRL));
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gpio_direction_input(IMX_GPIO_NR(1, 0));
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
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NO_PAD_CTRL));
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gpio_direction_input(IMX_GPIO_NR(1, 6));
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
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else
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ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
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return ret;
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}
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int board_mmc_init(struct bd_info *bis)
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{
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static const iomux_v3_cfg_t sd1_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
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PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
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};
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
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return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_iomux_fec();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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/*
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* Read the MAC address from FEC's registers PALR PAUR.
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* User is supposed to configure these registers when MAC address is known
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* from another source (fuse), but on TS4800, MAC address is not fused and
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* the bootrom configure these registers on startup.
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*/
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static int fec_get_mac_from_register(uint32_t base_addr)
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{
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unsigned char ethaddr[6];
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u32 reg_mac[2];
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int i;
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reg_mac[0] = in_be32(base_addr + 0xE4);
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reg_mac[1] = in_be32(base_addr + 0xE8);
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for(i = 0; i < 6; i++)
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ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF;
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if (is_valid_ethaddr(ethaddr)) {
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eth_env_set_enetaddr("ethaddr", ethaddr);
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return 0;
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}
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return -1;
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}
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#define TS4800_GPIO_FEC_PHY_RES IMX_GPIO_NR(2, 14)
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int board_eth_init(struct bd_info *bd)
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{
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int dev_id = -1;
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int phy_id = 0xFF;
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uint32_t addr = IMX_FEC_BASE;
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uint32_t base_mii;
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struct mii_dev *bus = NULL;
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struct phy_device *phydev = NULL;
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int ret;
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/* reset FEC phy */
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imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14);
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gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0);
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mdelay(1);
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gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1);
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mdelay(1);
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base_mii = addr;
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debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
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bus = fec_get_miibus(base_mii, dev_id);
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if (!bus)
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return -ENOMEM;
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phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII);
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if (!phydev) {
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free(bus);
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return -ENOMEM;
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}
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if (fec_get_mac_from_register(addr))
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printf("eth_init: failed to get MAC address\n");
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ret = fec_probe(bd, dev_id, addr, bus, phydev);
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if (ret) {
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free(phydev);
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free(bus);
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}
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return ret;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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int checkboard(void)
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{
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puts("Board: TS4800\n");
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return 0;
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}
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void hw_watchdog_reset(void)
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{
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struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE);
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/* feed the watchdog for another 10s */
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writew(0x2, &wtd->feed);
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}
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void hw_watchdog_init(void)
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{
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return;
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}
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