500 lines
12 KiB
C
500 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Texas Instruments' K3 SD Host Controller Interface
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <power-domain.h>
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#include <regmap.h>
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#include <sdhci.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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/* CTL_CFG Registers */
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#define CTL_CFG_2 0x14
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#define SLOTTYPE_MASK GENMASK(31, 30)
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#define SLOTTYPE_EMBEDDED BIT(30)
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/* PHY Registers */
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#define PHY_CTRL1 0x100
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#define PHY_CTRL2 0x104
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#define PHY_CTRL3 0x108
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#define PHY_CTRL4 0x10C
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#define PHY_CTRL5 0x110
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#define PHY_CTRL6 0x114
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#define PHY_STAT1 0x130
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#define PHY_STAT2 0x134
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#define IOMUX_ENABLE_SHIFT 31
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#define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
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#define OTAPDLYENA_SHIFT 20
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#define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
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#define OTAPDLYSEL_SHIFT 12
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#define OTAPDLYSEL_MASK GENMASK(15, 12)
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#define STRBSEL_SHIFT 24
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#define STRBSEL_4BIT_MASK GENMASK(27, 24)
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#define STRBSEL_8BIT_MASK GENMASK(31, 24)
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#define SEL50_SHIFT 8
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#define SEL50_MASK BIT(SEL50_SHIFT)
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#define SEL100_SHIFT 9
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#define SEL100_MASK BIT(SEL100_SHIFT)
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#define FREQSEL_SHIFT 8
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#define FREQSEL_MASK GENMASK(10, 8)
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#define DLL_TRIM_ICP_SHIFT 4
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#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
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#define DR_TY_SHIFT 20
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#define DR_TY_MASK GENMASK(22, 20)
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#define ENDLL_SHIFT 1
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#define ENDLL_MASK BIT(ENDLL_SHIFT)
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#define DLLRDY_SHIFT 0
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#define DLLRDY_MASK BIT(DLLRDY_SHIFT)
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#define PDB_SHIFT 0
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#define PDB_MASK BIT(PDB_SHIFT)
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#define CALDONE_SHIFT 1
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#define CALDONE_MASK BIT(CALDONE_SHIFT)
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#define RETRIM_SHIFT 17
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#define RETRIM_MASK BIT(RETRIM_SHIFT)
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#define DRIVER_STRENGTH_50_OHM 0x0
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#define DRIVER_STRENGTH_33_OHM 0x1
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#define DRIVER_STRENGTH_66_OHM 0x2
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#define DRIVER_STRENGTH_100_OHM 0x3
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#define DRIVER_STRENGTH_40_OHM 0x4
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#define AM654_SDHCI_MIN_FREQ 400000
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struct am654_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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struct regmap *base;
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bool non_removable;
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u32 otap_del_sel[11];
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u32 trm_icp;
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u32 drv_strength;
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u32 strb_sel;
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u32 flags;
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#define DLL_PRESENT (1 << 0)
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#define IOMUX_PRESENT (1 << 1)
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#define FREQSEL_2_BIT (1 << 2)
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#define STRBSEL_4_BIT (1 << 3)
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bool dll_on;
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};
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struct timing_data {
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const char *binding;
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u32 capability;
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};
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static const struct timing_data td[] = {
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[MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0},
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[MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)},
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[SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)},
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[UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)},
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[UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)},
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[UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)},
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[UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)},
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[UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)},
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[MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)},
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[MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)},
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[MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)},
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};
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struct am654_driver_data {
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const struct sdhci_ops *ops;
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u32 flags;
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};
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static void am654_sdhci_set_control_reg(struct sdhci_host *host)
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{
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struct mmc *mmc = (struct mmc *)host->mmc;
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u32 reg;
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if (IS_SD(host->mmc) &&
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mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
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reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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reg |= SDHCI_CTRL_VDD_180;
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sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
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}
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sdhci_set_uhs_timing(host);
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}
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static int am654_sdhci_set_ios_post(struct sdhci_host *host)
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{
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struct udevice *dev = host->mmc->dev;
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struct am654_sdhci_plat *plat = dev_get_platdata(dev);
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unsigned int speed = host->mmc->clock;
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int sel50, sel100, freqsel;
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u32 otap_del_sel;
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u32 mask, val;
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int ret;
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/* Reset SD Clock Enable */
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val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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val &= ~SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
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/* power off phy */
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if (plat->dll_on) {
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regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
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plat->dll_on = false;
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}
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/* restart clock */
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sdhci_set_clock(host->mmc, speed);
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/* switch phy back on */
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if (speed > AM654_SDHCI_MIN_FREQ) {
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otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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val = (1 << OTAPDLYENA_SHIFT) |
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(otap_del_sel << OTAPDLYSEL_SHIFT);
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/* Write to STRBSEL for HS400 speed mode */
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if (host->mmc->selected_mode == MMC_HS_400) {
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if (plat->flags & STRBSEL_4_BIT)
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mask |= STRBSEL_4BIT_MASK;
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else
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mask |= STRBSEL_8BIT_MASK;
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val |= plat->strb_sel << STRBSEL_SHIFT;
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}
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regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
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if (plat->flags & FREQSEL_2_BIT) {
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switch (speed) {
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case 200000000:
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sel50 = 0;
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sel100 = 0;
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break;
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case 100000000:
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sel50 = 0;
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sel100 = 1;
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break;
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default:
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sel50 = 1;
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sel100 = 0;
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}
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/* Configure PHY DLL frequency */
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mask = SEL50_MASK | SEL100_MASK;
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val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
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regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
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} else {
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switch (speed) {
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case 200000000:
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freqsel = 0x0;
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break;
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default:
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freqsel = 0x4;
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}
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regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
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freqsel << FREQSEL_SHIFT);
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}
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/* Enable DLL */
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regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
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0x1 << ENDLL_SHIFT);
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/*
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* Poll for DLL ready. Use a one second timeout.
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* Works in all experiments done so far
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*/
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ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
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val & DLLRDY_MASK, 1000, 1000000);
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if (ret)
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return ret;
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plat->dll_on = true;
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}
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return 0;
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}
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int am654_sdhci_init(struct am654_sdhci_plat *plat)
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{
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u32 ctl_cfg_2 = 0;
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u32 mask, val;
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int ret;
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/* Reset OTAP to default value */
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
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if (plat->flags & DLL_PRESENT) {
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regmap_read(plat->base, PHY_STAT1, &val);
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if (~val & CALDONE_MASK) {
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/* Calibrate IO lines */
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regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
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PDB_MASK);
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ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
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val, val & CALDONE_MASK,
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1, 20);
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if (ret)
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return ret;
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}
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/* Configure DLL TRIM */
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mask = DLL_TRIM_ICP_MASK;
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val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
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/* Configure DLL driver strength */
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mask |= DR_TY_MASK;
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val |= plat->drv_strength << DR_TY_SHIFT;
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regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
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}
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/* Enable pins by setting IO mux to 0 */
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if (plat->flags & IOMUX_PRESENT)
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regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
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/* Set slot type based on SD or eMMC */
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if (plat->non_removable)
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ctl_cfg_2 = SLOTTYPE_EMBEDDED;
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regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
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return 0;
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}
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#define MAX_SDCD_DEBOUNCE_TIME 2000
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static int am654_sdhci_deferred_probe(struct sdhci_host *host)
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{
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struct udevice *dev = host->mmc->dev;
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struct am654_sdhci_plat *plat = dev_get_platdata(dev);
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unsigned long start;
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int val;
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/*
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* The controller takes about 1 second to debounce the card detect line
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* and doesn't let us power on until that time is up. Instead of waiting
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* for 1 second at every stage, poll on the CARD_PRESENT bit upto a
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* maximum of 2 seconds to be safe..
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*/
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start = get_timer(0);
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do {
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if (get_timer(start) > MAX_SDCD_DEBOUNCE_TIME)
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return -ENOMEDIUM;
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val = mmc_getcd(host->mmc);
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} while (!val);
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am654_sdhci_init(plat);
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return sdhci_probe(dev);
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}
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const struct sdhci_ops am654_sdhci_ops = {
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.deferred_probe = am654_sdhci_deferred_probe,
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.set_ios_post = &am654_sdhci_set_ios_post,
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.set_control_reg = &am654_sdhci_set_control_reg,
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};
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const struct am654_driver_data am654_drv_data = {
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.ops = &am654_sdhci_ops,
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.flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT,
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};
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const struct am654_driver_data j721e_8bit_drv_data = {
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.ops = &am654_sdhci_ops,
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.flags = DLL_PRESENT,
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};
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static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
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{
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struct udevice *dev = host->mmc->dev;
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struct am654_sdhci_plat *plat = dev_get_platdata(dev);
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u32 otap_del_sel, mask, val;
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otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
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regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
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return 0;
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}
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const struct sdhci_ops j721e_4bit_sdhci_ops = {
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.deferred_probe = am654_sdhci_deferred_probe,
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.set_ios_post = &j721e_4bit_sdhci_set_ios_post,
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};
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const struct am654_driver_data j721e_4bit_drv_data = {
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.ops = &j721e_4bit_sdhci_ops,
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.flags = IOMUX_PRESENT,
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};
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static int sdhci_am654_get_otap_delay(struct udevice *dev,
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struct mmc_config *cfg)
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{
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struct am654_sdhci_plat *plat = dev_get_platdata(dev);
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int ret;
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int i;
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/* ti,otap-del-sel-legacy is mandatory */
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ret = dev_read_u32(dev, "ti,otap-del-sel-legacy",
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&plat->otap_del_sel[0]);
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if (ret)
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return ret;
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/*
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* Remove the corresponding capability if an otap-del-sel
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* value is not found
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*/
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for (i = MMC_HS; i <= MMC_HS_400; i++) {
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ret = dev_read_u32(dev, td[i].binding, &plat->otap_del_sel[i]);
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if (ret) {
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dev_dbg(dev, "Couldn't find %s\n", td[i].binding);
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/*
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* Remove the corresponding capability
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* if an otap-del-sel value is not found
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*/
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cfg->host_caps &= ~td[i].capability;
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}
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}
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return 0;
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}
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static int am654_sdhci_probe(struct udevice *dev)
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{
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struct am654_driver_data *drv_data =
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(struct am654_driver_data *)dev_get_driver_data(dev);
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struct am654_sdhci_plat *plat = dev_get_platdata(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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struct mmc_config *cfg = &plat->cfg;
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struct clk clk;
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unsigned long clock;
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int ret;
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ret = clk_get_by_name(dev, "clk_xin", &clk);
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if (ret) {
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dev_err(dev, "failed to get clock\n");
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return ret;
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}
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clock = clk_get_rate(&clk);
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if (IS_ERR_VALUE(clock)) {
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dev_err(dev, "failed to get rate\n");
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return clock;
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}
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host->max_clk = clock;
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host->mmc = &plat->mmc;
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host->mmc->dev = dev;
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ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
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AM654_SDHCI_MIN_FREQ);
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if (ret)
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return ret;
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ret = sdhci_am654_get_otap_delay(dev, cfg);
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if (ret)
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return ret;
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host->ops = drv_data->ops;
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host->mmc->priv = host;
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upriv->mmc = host->mmc;
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regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
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return 0;
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}
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static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
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{
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struct am654_sdhci_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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struct mmc_config *cfg = &plat->cfg;
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u32 drv_strength;
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int ret;
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host->name = dev->name;
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host->ioaddr = (void *)dev_read_addr(dev);
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plat->non_removable = dev_read_bool(dev, "non-removable");
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if (plat->flags & DLL_PRESENT) {
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ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
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if (ret)
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return ret;
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ret = dev_read_u32(dev, "ti,driver-strength-ohm",
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&drv_strength);
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if (ret)
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return ret;
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switch (drv_strength) {
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case 50:
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plat->drv_strength = DRIVER_STRENGTH_50_OHM;
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break;
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case 33:
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plat->drv_strength = DRIVER_STRENGTH_33_OHM;
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break;
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case 66:
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plat->drv_strength = DRIVER_STRENGTH_66_OHM;
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break;
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case 100:
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plat->drv_strength = DRIVER_STRENGTH_100_OHM;
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break;
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case 40:
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plat->drv_strength = DRIVER_STRENGTH_40_OHM;
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break;
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default:
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dev_err(dev, "Invalid driver strength\n");
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return -EINVAL;
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}
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}
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ret = mmc_of_parse(dev, cfg);
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if (ret)
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return ret;
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return 0;
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}
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static int am654_sdhci_bind(struct udevice *dev)
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{
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struct am654_driver_data *drv_data =
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(struct am654_driver_data *)dev_get_driver_data(dev);
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struct am654_sdhci_plat *plat = dev_get_platdata(dev);
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plat->flags = drv_data->flags;
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id am654_sdhci_ids[] = {
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{
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.compatible = "ti,am654-sdhci-5.1",
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.data = (ulong)&am654_drv_data,
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},
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{
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.compatible = "ti,j721e-sdhci-8bit",
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.data = (ulong)&j721e_8bit_drv_data,
|
|
},
|
|
{
|
|
.compatible = "ti,j721e-sdhci-4bit",
|
|
.data = (ulong)&j721e_4bit_drv_data,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(am654_sdhci_drv) = {
|
|
.name = "am654_sdhci",
|
|
.id = UCLASS_MMC,
|
|
.of_match = am654_sdhci_ids,
|
|
.ofdata_to_platdata = am654_sdhci_ofdata_to_platdata,
|
|
.ops = &sdhci_ops,
|
|
.bind = am654_sdhci_bind,
|
|
.probe = am654_sdhci_probe,
|
|
.priv_auto_alloc_size = sizeof(struct sdhci_host),
|
|
.platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat),
|
|
};
|