659 lines
16 KiB
C
659 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <env.h>
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <pci.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#define SROM_DLEVEL 0
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#undef UPDATE_SROM
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/* PCI Registers. */
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#define PCI_CFDA_PSM 0x43
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#define CFRV_RN 0x000000f0 /* Revision Number */
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#define WAKEUP 0x00 /* Power Saving Wakeup */
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#define SLEEP 0x80 /* Power Saving Sleep Mode */
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#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
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/* Ethernet chip registers. */
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#define DE4X5_BMR 0x000 /* Bus Mode Register */
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#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
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#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
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#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
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#define DE4X5_STS 0x028 /* Status Register */
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#define DE4X5_OMR 0x030 /* Operation Mode Register */
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#define DE4X5_SICR 0x068 /* SIA Connectivity Register */
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#define DE4X5_APROM 0x048 /* Ethernet Address PROM */
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/* Register bits. */
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#define BMR_SWR 0x00000001 /* Software Reset */
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#define STS_TS 0x00700000 /* Transmit Process State */
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#define STS_RS 0x000e0000 /* Receive Process State */
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#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
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#define OMR_SR 0x00000002 /* Start/Stop Receive */
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#define OMR_PS 0x00040000 /* Port Select */
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#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
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#define OMR_PM 0x00000080 /* Pass All Multicast */
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/* Descriptor bits. */
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#define R_OWN 0x80000000 /* Own Bit */
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#define RD_RER 0x02000000 /* Receive End Of Ring */
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#define RD_LS 0x00000100 /* Last Descriptor */
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#define RD_ES 0x00008000 /* Error Summary */
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#define TD_TER 0x02000000 /* Transmit End Of Ring */
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#define T_OWN 0x80000000 /* Own Bit */
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#define TD_LS 0x40000000 /* Last Segment */
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#define TD_FS 0x20000000 /* First Segment */
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#define TD_ES 0x00008000 /* Error Summary */
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#define TD_SET 0x08000000 /* Setup Packet */
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/* The EEPROM commands include the alway-set leading bit. */
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#define SROM_WRITE_CMD 5
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#define SROM_READ_CMD 6
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#define SROM_ERASE_CMD 7
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#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
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#define SROM_RD 0x00004000 /* Read from Boot ROM */
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#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
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#define EE_WRITE_0 0x4801
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#define EE_WRITE_1 0x4805
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#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
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#define SROM_SR 0x00000800 /* Select Serial ROM when set */
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#define DT_IN 0x00000004 /* Serial Data In */
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#define DT_CLK 0x00000002 /* Serial ROM Clock */
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#define DT_CS 0x00000001 /* Serial ROM Chip Select */
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#define POLL_DEMAND 1
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#if defined(CONFIG_E500)
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#define phys_to_bus(a) (a)
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#else
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#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
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#endif
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#define NUM_RX_DESC PKTBUFSRX
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#define NUM_TX_DESC 1 /* Number of TX descriptors */
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#define RX_BUFF_SZ PKTSIZE_ALIGN
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#define TOUT_LOOP 1000000
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#define SETUP_FRAME_LEN 192
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struct de4x5_desc {
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volatile s32 status;
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u32 des1;
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u32 buf;
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u32 next;
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};
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/* RX and TX descriptor ring */
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static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
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static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
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static int rx_new; /* RX descriptor ring pointer */
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static int tx_new; /* TX descriptor ring pointer */
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static char rx_ring_size;
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static char tx_ring_size;
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static u32 dc2114x_inl(struct eth_device *dev, u32 addr)
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{
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return le32_to_cpu(*(volatile u32 *)(addr + dev->iobase));
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}
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static void dc2114x_outl(struct eth_device *dev, u32 command, u32 addr)
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{
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*(volatile u32 *)(addr + dev->iobase) = cpu_to_le32(command);
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}
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static void reset_de4x5(struct eth_device *dev)
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{
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u32 i;
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i = dc2114x_inl(dev, DE4X5_BMR);
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mdelay(1);
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dc2114x_outl(dev, i | BMR_SWR, DE4X5_BMR);
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mdelay(1);
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dc2114x_outl(dev, i, DE4X5_BMR);
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mdelay(1);
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for (i = 0; i < 5; i++) {
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dc2114x_inl(dev, DE4X5_BMR);
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mdelay(10);
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}
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mdelay(1);
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}
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static void start_de4x5(struct eth_device *dev)
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{
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u32 omr;
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omr = dc2114x_inl(dev, DE4X5_OMR);
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omr |= OMR_ST | OMR_SR;
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dc2114x_outl(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */
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}
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static void stop_de4x5(struct eth_device *dev)
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{
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u32 omr;
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omr = dc2114x_inl(dev, DE4X5_OMR);
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omr &= ~(OMR_ST | OMR_SR);
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dc2114x_outl(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */
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}
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/* SROM Read and write routines. */
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static void sendto_srom(struct eth_device *dev, u_int command, u_long addr)
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{
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dc2114x_outl(dev, command, addr);
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udelay(1);
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}
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static int getfrom_srom(struct eth_device *dev, u_long addr)
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{
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u32 tmp = dc2114x_inl(dev, addr);
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udelay(1);
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return tmp;
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}
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/* Note: this routine returns extra data bits for size detection. */
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static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location,
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int addr_len)
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{
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int read_cmd = location | (SROM_READ_CMD << addr_len);
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unsigned int retval = 0;
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int i;
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sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
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sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
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debug_cond(SROM_DLEVEL >= 1, " EEPROM read at %d ", location);
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/* Shift the read command bits out. */
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for (i = 4 + addr_len; i >= 0; i--) {
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short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
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sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval,
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ioaddr);
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udelay(10);
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sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK,
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ioaddr);
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udelay(10);
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debug_cond(SROM_DLEVEL >= 2, "%X",
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getfrom_srom(dev, ioaddr) & 15);
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retval = (retval << 1) |
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!!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
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}
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sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
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debug_cond(SROM_DLEVEL >= 2, " :%X:", getfrom_srom(dev, ioaddr) & 15);
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for (i = 16; i > 0; i--) {
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sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
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udelay(10);
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debug_cond(SROM_DLEVEL >= 2, "%X",
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getfrom_srom(dev, ioaddr) & 15);
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retval = (retval << 1) |
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!!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
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sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
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udelay(10);
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}
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/* Terminate the EEPROM access. */
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sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
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debug_cond(SROM_DLEVEL >= 2, " EEPROM value at %d is %5.5x.\n",
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location, retval);
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return retval;
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}
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/*
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* This executes a generic EEPROM command, typically a write or write
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* enable. It returns the data output from the EEPROM, and thus may
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* also be used for reads.
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*/
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static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd,
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int cmd_len)
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{
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unsigned int retval = 0;
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debug_cond(SROM_DLEVEL >= 1, " EEPROM op 0x%x: ", cmd);
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sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
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/* Shift the command bits out. */
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do {
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short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
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sendto_srom(dev, dataval, ioaddr);
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udelay(10);
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debug_cond(SROM_DLEVEL >= 2, "%X",
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getfrom_srom(dev, ioaddr) & 15);
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sendto_srom(dev, dataval | DT_CLK, ioaddr);
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udelay(10);
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retval = (retval << 1) |
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!!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
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} while (--cmd_len >= 0);
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sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
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/* Terminate the EEPROM access. */
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sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
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debug_cond(SROM_DLEVEL >= 1, " EEPROM result is 0x%5.5x.\n", retval);
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return retval;
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}
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static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
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{
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int ee_addr_size;
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ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
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return do_eeprom_cmd(dev, ioaddr, 0xffff |
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(((SROM_READ_CMD << ee_addr_size) | index) << 16),
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3 + ee_addr_size + 16);
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}
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#ifdef UPDATE_SROM
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static int write_srom(struct eth_device *dev, u_long ioaddr, int index,
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int new_value)
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{
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unsigned short newval;
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int ee_addr_size;
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int i;
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ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
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udelay(10 * 1000); /* test-only */
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debug_cond(SROM_DLEVEL >= 1, "ee_addr_size=%d.\n", ee_addr_size);
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debug_cond(SROM_DLEVEL >= 1,
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"Writing new entry 0x%4.4x to offset %d.\n",
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new_value, index);
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/* Enable programming modes. */
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do_eeprom_cmd(dev, ioaddr, 0x4f << (ee_addr_size - 4),
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3 + ee_addr_size);
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/* Do the actual write. */
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do_eeprom_cmd(dev, ioaddr, new_value |
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(((SROM_WRITE_CMD << ee_addr_size) | index) << 16),
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3 + ee_addr_size + 16);
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/* Poll for write finished. */
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sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
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for (i = 0; i < 10000; i++) { /* Typical 2000 ticks */
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if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
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break;
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}
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debug_cond(SROM_DLEVEL >= 1, " Write finished after %d ticks.\n", i);
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/* Disable programming. */
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do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size - 4)),
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3 + ee_addr_size);
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/* And read the result. */
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newval = do_eeprom_cmd(dev, ioaddr,
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(((SROM_READ_CMD << ee_addr_size) | index) << 16)
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| 0xffff, 3 + ee_addr_size + 16);
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debug_cond(SROM_DLEVEL >= 1, " New value at offset %d is %4.4x.\n",
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index, newval);
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return 1;
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}
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static void update_srom(struct eth_device *dev, struct bd_info *bis)
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{
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static unsigned short eeprom[0x40] = {
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0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
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0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
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0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
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0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
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0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
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0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
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0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
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0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
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0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
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0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
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0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
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0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
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0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
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0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
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0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
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0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
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};
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uchar enetaddr[6];
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int i;
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/* Ethernet Addr... */
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if (!eth_env_get_enetaddr("ethaddr", enetaddr))
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return;
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eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
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eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
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eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
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for (i = 0; i < 0x40; i++)
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write_srom(dev, DE4X5_APROM, i, eeprom[i]);
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}
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#endif /* UPDATE_SROM */
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static void send_setup_frame(struct eth_device *dev, struct bd_info *bis)
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{
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char setup_frame[SETUP_FRAME_LEN];
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char *pa = &setup_frame[0];
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int i;
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memset(pa, 0xff, SETUP_FRAME_LEN);
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for (i = 0; i < ETH_ALEN; i++) {
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*(pa + (i & 1)) = dev->enetaddr[i];
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if (i & 0x01)
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pa += 4;
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}
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for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i < TOUT_LOOP)
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continue;
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printf("%s: tx error buffer not ready\n", dev->name);
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return;
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}
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tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0]));
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tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
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tx_ring[tx_new].status = cpu_to_le32(T_OWN);
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dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
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for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i < TOUT_LOOP)
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continue;
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printf("%s: tx buffer not ready\n", dev->name);
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return;
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}
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if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
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printf("TX error status2 = 0x%08X\n",
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le32_to_cpu(tx_ring[tx_new].status));
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}
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tx_new = (tx_new + 1) % NUM_TX_DESC;
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}
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static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
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{
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int status = -1;
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int i;
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if (length <= 0) {
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printf("%s: bad packet size: %d\n", dev->name, length);
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goto done;
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}
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for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i < TOUT_LOOP)
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continue;
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printf("%s: tx error buffer not ready\n", dev->name);
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goto done;
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}
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tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet));
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tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
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tx_ring[tx_new].status = cpu_to_le32(T_OWN);
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dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
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for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i < TOUT_LOOP)
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continue;
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printf(".%s: tx buffer not ready\n", dev->name);
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goto done;
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}
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if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
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tx_ring[tx_new].status = 0x0;
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goto done;
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}
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status = length;
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done:
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tx_new = (tx_new + 1) % NUM_TX_DESC;
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return status;
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}
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static int dc21x4x_recv(struct eth_device *dev)
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{
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int length = 0;
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u32 status;
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while (true) {
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status = le32_to_cpu(rx_ring[rx_new].status);
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if (status & R_OWN)
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break;
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if (status & RD_LS) {
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/* Valid frame status. */
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if (status & RD_ES) {
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/* There was an error. */
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printf("RX error status = 0x%08X\n", status);
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} else {
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/* A valid frame received. */
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length = (le32_to_cpu(rx_ring[rx_new].status)
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>> 16);
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/* Pass the packet up to the protocol layers */
|
|
net_process_received_packet
|
|
(net_rx_packets[rx_new], length - 4);
|
|
}
|
|
|
|
/*
|
|
* Change buffer ownership for this frame,
|
|
* back to the adapter.
|
|
*/
|
|
rx_ring[rx_new].status = cpu_to_le32(R_OWN);
|
|
}
|
|
|
|
/* Update entry information. */
|
|
rx_new = (rx_new + 1) % rx_ring_size;
|
|
}
|
|
|
|
return length;
|
|
}
|
|
|
|
static int dc21x4x_init(struct eth_device *dev, struct bd_info *bis)
|
|
{
|
|
int i;
|
|
int devbusfn = (int)dev->priv;
|
|
|
|
/* Ensure we're not sleeping. */
|
|
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
|
|
|
|
reset_de4x5(dev);
|
|
|
|
if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) {
|
|
printf("Error: Cannot reset ethernet controller.\n");
|
|
return -1;
|
|
}
|
|
|
|
dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
|
|
|
|
for (i = 0; i < NUM_RX_DESC; i++) {
|
|
rx_ring[i].status = cpu_to_le32(R_OWN);
|
|
rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
|
|
rx_ring[i].buf =
|
|
cpu_to_le32(phys_to_bus((u32)net_rx_packets[i]));
|
|
rx_ring[i].next = 0;
|
|
}
|
|
|
|
for (i = 0; i < NUM_TX_DESC; i++) {
|
|
tx_ring[i].status = 0;
|
|
tx_ring[i].des1 = 0;
|
|
tx_ring[i].buf = 0;
|
|
tx_ring[i].next = 0;
|
|
}
|
|
|
|
rx_ring_size = NUM_RX_DESC;
|
|
tx_ring_size = NUM_TX_DESC;
|
|
|
|
/* Write the end of list marker to the descriptor lists. */
|
|
rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
|
|
tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
|
|
|
|
/* Tell the adapter where the TX/RX rings are located. */
|
|
dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA);
|
|
dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA);
|
|
|
|
start_de4x5(dev);
|
|
|
|
tx_new = 0;
|
|
rx_new = 0;
|
|
|
|
send_setup_frame(dev, bis);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dc21x4x_halt(struct eth_device *dev)
|
|
{
|
|
int devbusfn = (int)dev->priv;
|
|
|
|
stop_de4x5(dev);
|
|
dc2114x_outl(dev, 0, DE4X5_SICR);
|
|
|
|
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
|
|
}
|
|
|
|
static void read_hw_addr(struct eth_device *dev, struct bd_info *bis)
|
|
{
|
|
u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
|
|
int i, j = 0;
|
|
|
|
for (i = 0; i < (ETH_ALEN >> 1); i++) {
|
|
tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i);
|
|
*p = le16_to_cpu(tmp);
|
|
j += *p++;
|
|
}
|
|
|
|
if (!j || j == 0x2fffd) {
|
|
memset(dev->enetaddr, 0, ETH_ALEN);
|
|
debug("Warning: can't read HW address from SROM.\n");
|
|
#ifdef UPDATE_SROM
|
|
update_srom(dev, bis);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
static struct pci_device_id supported[] = {
|
|
{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
|
|
{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
|
|
{ }
|
|
};
|
|
|
|
int dc21x4x_initialize(struct bd_info *bis)
|
|
{
|
|
struct eth_device *dev;
|
|
unsigned short status;
|
|
unsigned char timer;
|
|
unsigned int iobase;
|
|
int card_number = 0;
|
|
pci_dev_t devbusfn;
|
|
unsigned int cfrv;
|
|
int idx = 0;
|
|
|
|
while (1) {
|
|
devbusfn = pci_find_devices(supported, idx++);
|
|
if (devbusfn == -1)
|
|
break;
|
|
|
|
/* Get the chip configuration revision register. */
|
|
pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
|
|
|
|
if ((cfrv & CFRV_RN) < DC2114x_BRK) {
|
|
printf("Error: The chip is not DC21143.\n");
|
|
continue;
|
|
}
|
|
|
|
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
|
|
status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
|
pci_write_config_word(devbusfn, PCI_COMMAND, status);
|
|
|
|
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
|
|
if (!(status & PCI_COMMAND_MEMORY)) {
|
|
printf("Error: Can not enable MEMORY access.\n");
|
|
continue;
|
|
}
|
|
|
|
if (!(status & PCI_COMMAND_MASTER)) {
|
|
printf("Error: Can not enable Bus Mastering.\n");
|
|
continue;
|
|
}
|
|
|
|
/* Check the latency timer for values >= 0x60. */
|
|
pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
|
|
|
|
if (timer < 0x60) {
|
|
pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
|
|
0x60);
|
|
}
|
|
|
|
/* read BAR for memory space access */
|
|
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
|
|
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
|
|
debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
|
|
|
|
dev = (struct eth_device *)malloc(sizeof(*dev));
|
|
if (!dev) {
|
|
printf("Can not allocalte memory of dc21x4x\n");
|
|
break;
|
|
}
|
|
|
|
memset(dev, 0, sizeof(*dev));
|
|
|
|
sprintf(dev->name, "dc21x4x#%d", card_number);
|
|
|
|
dev->iobase = pci_mem_to_phys(devbusfn, iobase);
|
|
dev->priv = (void *)devbusfn;
|
|
dev->init = dc21x4x_init;
|
|
dev->halt = dc21x4x_halt;
|
|
dev->send = dc21x4x_send;
|
|
dev->recv = dc21x4x_recv;
|
|
|
|
/* Ensure we're not sleeping. */
|
|
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
|
|
|
|
udelay(10 * 1000);
|
|
|
|
read_hw_addr(dev, bis);
|
|
|
|
eth_register(dev);
|
|
|
|
card_number++;
|
|
}
|
|
|
|
return card_number;
|
|
}
|