677 lines
15 KiB
C
677 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Micrel KS8851_MLL 16bit Network driver
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* Copyright (c) 2011 Roberto Cerati <roberto.cerati@bticino.it>
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*/
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#include <log.h>
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#include <asm/io.h>
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include <linux/delay.h>
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#include "ks8851_mll.h"
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#define DRIVERNAME "ks8851_mll"
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#define RX_BUF_SIZE 2000
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/*
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* struct ks_net - KS8851 driver private data
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* @dev : legacy non-DM ethernet device structure
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* @iobase : register base
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* @bus_width : i/o bus width.
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* @sharedbus : Multipex(addr and data bus) mode indicator.
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* @extra_byte : number of extra byte prepended rx pkt.
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*/
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struct ks_net {
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#ifndef CONFIG_DM_ETH
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struct eth_device dev;
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#endif
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phys_addr_t iobase;
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int bus_width;
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u16 sharedbus;
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u16 rxfc;
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u8 extra_byte;
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};
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#define BE3 0x8000 /* Byte Enable 3 */
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#define BE2 0x4000 /* Byte Enable 2 */
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#define BE1 0x2000 /* Byte Enable 1 */
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#define BE0 0x1000 /* Byte Enable 0 */
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static u8 ks_rdreg8(struct ks_net *ks, u16 offset)
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{
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u8 shift_bit = offset & 0x03;
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u8 shift_data = (offset & 1) << 3;
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writew(offset | (BE0 << shift_bit), ks->iobase + 2);
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return (u8)(readw(ks->iobase) >> shift_data);
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}
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static u16 ks_rdreg16(struct ks_net *ks, u16 offset)
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{
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writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
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return readw(ks->iobase);
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}
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static void ks_wrreg16(struct ks_net *ks, u16 offset, u16 val)
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{
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writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
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writew(val, ks->iobase);
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}
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/*
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* ks_inblk - read a block of data from QMU. This is called after sudo DMA mode
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* enabled.
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* @ks: The chip state
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* @wptr: buffer address to save data
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* @len: length in byte to read
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*/
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static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
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{
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len >>= 1;
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while (len--)
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*wptr++ = readw(ks->iobase);
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}
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/*
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* ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
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* @ks: The chip information
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* @wptr: buffer address
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* @len: length in byte to write
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*/
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static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
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{
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len >>= 1;
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while (len--)
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writew(*wptr++, ks->iobase);
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}
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static void ks_enable_int(struct ks_net *ks)
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{
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ks_wrreg16(ks, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
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}
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static void ks_set_powermode(struct ks_net *ks, unsigned int pwrmode)
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{
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unsigned int pmecr;
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ks_rdreg16(ks, KS_GRR);
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pmecr = ks_rdreg16(ks, KS_PMECR);
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pmecr &= ~PMECR_PM_MASK;
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pmecr |= pwrmode;
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ks_wrreg16(ks, KS_PMECR, pmecr);
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}
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/*
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* ks_read_config - read chip configuration of bus width.
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* @ks: The chip information
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*/
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static void ks_read_config(struct ks_net *ks)
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{
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u16 reg_data = 0;
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/* Regardless of bus width, 8 bit read should always work. */
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reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
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reg_data |= ks_rdreg8(ks, KS_CCR + 1) << 8;
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/* addr/data bus are multiplexed */
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ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
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/*
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* There are garbage data when reading data from QMU,
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* depending on bus-width.
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*/
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if (reg_data & CCR_8BIT) {
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ks->bus_width = ENUM_BUS_8BIT;
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ks->extra_byte = 1;
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} else if (reg_data & CCR_16BIT) {
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ks->bus_width = ENUM_BUS_16BIT;
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ks->extra_byte = 2;
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} else {
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ks->bus_width = ENUM_BUS_32BIT;
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ks->extra_byte = 4;
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}
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}
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/*
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* ks_soft_reset - issue one of the soft reset to the device
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* @ks: The device state.
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* @op: The bit(s) to set in the GRR
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*
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* Issue the relevant soft-reset command to the device's GRR register
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* specified by @op.
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*
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* Note, the delays are in there as a caution to ensure that the reset
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* has time to take effect and then complete. Since the datasheet does
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* not currently specify the exact sequence, we have chosen something
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* that seems to work with our device.
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*/
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static void ks_soft_reset(struct ks_net *ks, unsigned int op)
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{
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/* Disable interrupt first */
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ks_wrreg16(ks, KS_IER, 0x0000);
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ks_wrreg16(ks, KS_GRR, op);
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mdelay(10); /* wait a short time to effect reset */
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ks_wrreg16(ks, KS_GRR, 0);
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mdelay(1); /* wait for condition to clear */
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}
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void ks_enable_qmu(struct ks_net *ks)
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{
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u16 w;
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w = ks_rdreg16(ks, KS_TXCR);
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/* Enables QMU Transmit (TXCR). */
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ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
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/* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
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w = ks_rdreg16(ks, KS_RXQCR);
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ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
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/* Enables QMU Receive (RXCR1). */
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w = ks_rdreg16(ks, KS_RXCR1);
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ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
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}
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static void ks_disable_qmu(struct ks_net *ks)
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{
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u16 w;
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w = ks_rdreg16(ks, KS_TXCR);
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/* Disables QMU Transmit (TXCR). */
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w &= ~TXCR_TXE;
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ks_wrreg16(ks, KS_TXCR, w);
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/* Disables QMU Receive (RXCR1). */
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w = ks_rdreg16(ks, KS_RXCR1);
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w &= ~RXCR1_RXE;
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ks_wrreg16(ks, KS_RXCR1, w);
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}
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static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
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{
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u32 r = ks->extra_byte & 0x1;
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u32 w = ks->extra_byte - r;
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/* 1. set sudo DMA mode */
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ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
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ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
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/*
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* 2. read prepend data
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*
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* read 4 + extra bytes and discard them.
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* extra bytes for dummy, 2 for status, 2 for len
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*/
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if (r)
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ks_rdreg8(ks, 0);
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ks_inblk(ks, buf, w + 2 + 2);
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/* 3. read pkt data */
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ks_inblk(ks, buf, ALIGN(len, 4));
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/* 4. reset sudo DMA Mode */
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ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
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}
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static int ks_rcv(struct ks_net *ks, uchar *data)
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{
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u16 sts, len;
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if (!ks->rxfc)
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ks->rxfc = ks_rdreg16(ks, KS_RXFCTR) >> 8;
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if (!ks->rxfc)
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return 0;
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/* Checking Received packet status */
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sts = ks_rdreg16(ks, KS_RXFHSR);
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/* Get packet len from hardware */
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len = ks_rdreg16(ks, KS_RXFHBCR);
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if ((sts & RXFSHR_RXFV) && len && (len < RX_BUF_SIZE)) {
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/* read data block including CRC 4 bytes */
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ks_read_qmu(ks, (u16 *)data, len);
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ks->rxfc--;
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return len - 4;
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}
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ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
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printf(DRIVERNAME ": bad packet\n");
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return 0;
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}
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/*
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* ks_read_selftest - read the selftest memory info.
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* @ks: The device state
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*
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* Read and check the TX/RX memory selftest information.
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*/
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static int ks_read_selftest(struct ks_net *ks)
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{
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u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
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u16 mbir;
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int ret = 0;
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mbir = ks_rdreg16(ks, KS_MBIR);
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if ((mbir & both_done) != both_done) {
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printf(DRIVERNAME ": Memory selftest not finished\n");
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return 0;
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}
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if (mbir & MBIR_TXMBFA) {
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printf(DRIVERNAME ": TX memory selftest fails\n");
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ret |= 1;
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}
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if (mbir & MBIR_RXMBFA) {
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printf(DRIVERNAME ": RX memory selftest fails\n");
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ret |= 2;
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}
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debug(DRIVERNAME ": the selftest passes\n");
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return ret;
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}
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static void ks_setup(struct ks_net *ks)
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{
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u16 w;
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/* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
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ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
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/* Setup Receive Frame Data Pointer Auto-Increment */
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ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
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/* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
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ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
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/* Setup RxQ Command Control (RXQCR) */
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ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
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/*
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* set the force mode to half duplex, default is full duplex
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* because if the auto-negotiation fails, most switch uses
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* half-duplex.
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*/
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w = ks_rdreg16(ks, KS_P1MBCR);
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w &= ~P1MBCR_FORCE_FDX;
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ks_wrreg16(ks, KS_P1MBCR, w);
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w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
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ks_wrreg16(ks, KS_TXCR, w);
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w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
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/* Normal mode */
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w |= RXCR1_RXPAFMA;
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ks_wrreg16(ks, KS_RXCR1, w);
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}
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static void ks_setup_int(struct ks_net *ks)
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{
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/* Clear the interrupts status of the hardware. */
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ks_wrreg16(ks, KS_ISR, 0xffff);
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}
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static int ks8851_mll_detect_chip(struct ks_net *ks)
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{
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unsigned short val;
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ks_read_config(ks);
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val = ks_rdreg16(ks, KS_CIDER);
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if (val == 0xffff) {
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/* Special case -- no chip present */
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printf(DRIVERNAME ": is chip mounted ?\n");
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return -1;
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} else if ((val & 0xfff0) != CIDER_ID) {
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printf(DRIVERNAME ": Invalid chip id 0x%04x\n", val);
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return -1;
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}
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debug("Read back KS8851 id 0x%x\n", val);
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if ((val & 0xfff0) != CIDER_ID) {
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printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
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return -1;
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}
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return 0;
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}
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static void ks8851_mll_reset(struct ks_net *ks)
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{
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/* wake up powermode to normal mode */
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ks_set_powermode(ks, PMECR_PM_NORMAL);
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mdelay(1); /* wait for normal mode to take effect */
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/* Disable interrupt and reset */
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ks_soft_reset(ks, GRR_GSR);
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/* turn off the IRQs and ack any outstanding */
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ks_wrreg16(ks, KS_IER, 0x0000);
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ks_wrreg16(ks, KS_ISR, 0xffff);
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/* shutdown RX/TX QMU */
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ks_disable_qmu(ks);
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}
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static void ks8851_mll_phy_configure(struct ks_net *ks)
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{
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u16 data;
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ks_setup(ks);
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ks_setup_int(ks);
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/* Probing the phy */
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data = ks_rdreg16(ks, KS_OBCR);
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ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
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debug(DRIVERNAME ": phy initialized\n");
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}
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static void ks8851_mll_enable(struct ks_net *ks)
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{
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ks_wrreg16(ks, KS_ISR, 0xffff);
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ks_enable_int(ks);
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ks_enable_qmu(ks);
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}
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static int ks8851_mll_init_common(struct ks_net *ks)
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{
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if (ks_read_selftest(ks)) {
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printf(DRIVERNAME ": Selftest failed\n");
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return -1;
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}
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ks8851_mll_reset(ks);
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/* Configure the PHY, initialize the link state */
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ks8851_mll_phy_configure(ks);
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ks->rxfc = 0;
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/* Turn on Tx + Rx */
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ks8851_mll_enable(ks);
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return 0;
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}
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static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
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{
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__le16 txw[2];
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/* start header at txb[0] to align txw entries */
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txw[0] = 0;
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txw[1] = cpu_to_le16(len);
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/* 1. set sudo-DMA mode */
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ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
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ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
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/* 2. write status/length info */
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ks_outblk(ks, txw, 4);
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/* 3. write pkt data */
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ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
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/* 4. reset sudo-DMA mode */
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ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
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/* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
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ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
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/* 6. wait until TXQCR_METFE is auto-cleared */
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do { } while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE);
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}
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static int ks8851_mll_send_common(struct ks_net *ks, void *packet, int length)
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{
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u8 *data = (u8 *)packet;
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u16 tmplen = (u16)length;
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u16 retv;
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/*
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* Extra space are required:
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* 4 byte for alignment, 4 for status/length, 4 for CRC
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*/
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retv = ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
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if (retv >= tmplen + 12) {
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ks_write_qmu(ks, data, tmplen);
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return 0;
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}
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printf(DRIVERNAME ": failed to send packet: No buffer\n");
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return -1;
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}
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static void ks8851_mll_halt_common(struct ks_net *ks)
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{
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ks8851_mll_reset(ks);
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}
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/*
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* Maximum receive ring size; that is, the number of packets
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* we can buffer before overflow happens. Basically, this just
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* needs to be enough to prevent a packet being discarded while
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* we are processing the previous one.
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*/
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static int ks8851_mll_recv_common(struct ks_net *ks, uchar *data)
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{
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u16 status;
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int ret = 0;
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status = ks_rdreg16(ks, KS_ISR);
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ks_wrreg16(ks, KS_ISR, status);
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if (ks->rxfc || (status & IRQ_RXI))
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ret = ks_rcv(ks, data);
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if (status & IRQ_LDI) {
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u16 pmecr = ks_rdreg16(ks, KS_PMECR);
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pmecr &= ~PMECR_WKEVT_MASK;
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ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
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}
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return ret;
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}
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static void ks8851_mll_write_hwaddr_common(struct ks_net *ks, u8 enetaddr[6])
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{
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u16 addrl, addrm, addrh;
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addrh = (enetaddr[0] << 8) | enetaddr[1];
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addrm = (enetaddr[2] << 8) | enetaddr[3];
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addrl = (enetaddr[4] << 8) | enetaddr[5];
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ks_wrreg16(ks, KS_MARH, addrh);
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ks_wrreg16(ks, KS_MARM, addrm);
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ks_wrreg16(ks, KS_MARL, addrl);
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}
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#ifndef CONFIG_DM_ETH
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static int ks8851_mll_init(struct eth_device *dev, struct bd_info *bd)
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{
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struct ks_net *ks = container_of(dev, struct ks_net, dev);
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|
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return ks8851_mll_init_common(ks);
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}
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|
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static void ks8851_mll_halt(struct eth_device *dev)
|
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{
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struct ks_net *ks = container_of(dev, struct ks_net, dev);
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|
|
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ks8851_mll_halt_common(ks);
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}
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|
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static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
|
|
{
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struct ks_net *ks = container_of(dev, struct ks_net, dev);
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|
|
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return ks8851_mll_send_common(ks, packet, length);
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}
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|
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static int ks8851_mll_recv(struct eth_device *dev)
|
|
{
|
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struct ks_net *ks = container_of(dev, struct ks_net, dev);
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int ret;
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|
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ret = ks8851_mll_recv_common(ks, net_rx_packets[0]);
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if (ret)
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net_process_received_packet(net_rx_packets[0], ret);
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|
|
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return ret;
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}
|
|
|
|
static int ks8851_mll_write_hwaddr(struct eth_device *dev)
|
|
{
|
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struct ks_net *ks = container_of(dev, struct ks_net, dev);
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|
|
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ks8851_mll_write_hwaddr_common(ks, ks->dev.enetaddr);
|
|
|
|
return 0;
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|
}
|
|
|
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int ks8851_mll_initialize(u8 dev_num, int base_addr)
|
|
{
|
|
struct ks_net *ks;
|
|
|
|
ks = calloc(1, sizeof(*ks));
|
|
if (!ks)
|
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return -ENOMEM;
|
|
|
|
ks->iobase = base_addr;
|
|
|
|
/* Try to detect chip. Will fail if not present. */
|
|
if (ks8851_mll_detect_chip(ks)) {
|
|
free(ks);
|
|
return -1;
|
|
}
|
|
|
|
ks->dev.init = ks8851_mll_init;
|
|
ks->dev.halt = ks8851_mll_halt;
|
|
ks->dev.send = ks8851_mll_send;
|
|
ks->dev.recv = ks8851_mll_recv;
|
|
ks->dev.write_hwaddr = ks8851_mll_write_hwaddr;
|
|
sprintf(ks->dev.name, "%s-%hu", DRIVERNAME, dev_num);
|
|
|
|
eth_register(&ks->dev);
|
|
|
|
return 0;
|
|
}
|
|
#else /* ifdef CONFIG_DM_ETH */
|
|
static int ks8851_start(struct udevice *dev)
|
|
{
|
|
struct ks_net *ks = dev_get_priv(dev);
|
|
|
|
return ks8851_mll_init_common(ks);
|
|
}
|
|
|
|
static void ks8851_stop(struct udevice *dev)
|
|
{
|
|
struct ks_net *ks = dev_get_priv(dev);
|
|
|
|
ks8851_mll_halt_common(ks);
|
|
}
|
|
|
|
static int ks8851_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct ks_net *ks = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ret = ks8851_mll_send_common(ks, packet, length);
|
|
|
|
return ret ? 0 : -ETIMEDOUT;
|
|
}
|
|
|
|
static int ks8851_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct ks_net *ks = dev_get_priv(dev);
|
|
uchar *data = net_rx_packets[0];
|
|
int ret;
|
|
|
|
ret = ks8851_mll_recv_common(ks, data);
|
|
if (ret)
|
|
*packetp = (void *)data;
|
|
|
|
return ret ? ret : -EAGAIN;
|
|
}
|
|
|
|
static int ks8851_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct ks_net *ks = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
|
|
ks8851_mll_write_hwaddr_common(ks, pdata->enetaddr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ks8851_bind(struct udevice *dev)
|
|
{
|
|
return device_set_name(dev, dev->name);
|
|
}
|
|
|
|
static int ks8851_probe(struct udevice *dev)
|
|
{
|
|
struct ks_net *ks = dev_get_priv(dev);
|
|
|
|
/* Try to detect chip. Will fail if not present. */
|
|
ks8851_mll_detect_chip(ks);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ks8851_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct ks_net *ks = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
|
|
pdata->iobase = devfdt_get_addr(dev);
|
|
ks->iobase = pdata->iobase;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops ks8851_ops = {
|
|
.start = ks8851_start,
|
|
.stop = ks8851_stop,
|
|
.send = ks8851_send,
|
|
.recv = ks8851_recv,
|
|
.write_hwaddr = ks8851_write_hwaddr,
|
|
};
|
|
|
|
static const struct udevice_id ks8851_ids[] = {
|
|
{ .compatible = "micrel,ks8851-mll" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(ks8851) = {
|
|
.name = "eth_ks8851",
|
|
.id = UCLASS_ETH,
|
|
.of_match = ks8851_ids,
|
|
.bind = ks8851_bind,
|
|
.ofdata_to_platdata = ks8851_ofdata_to_platdata,
|
|
.probe = ks8851_probe,
|
|
.ops = &ks8851_ops,
|
|
.priv_auto_alloc_size = sizeof(struct ks_net),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|
|
#endif
|