304 lines
6.8 KiB
C
304 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 MediaTek, Inc.
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* Authors: Chunfeng Yun <chunfeng.yun@mediatek.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <dm/devres.h>
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#include <generic-phy.h>
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#include <malloc.h>
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#include <usb.h>
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#include <linux/errno.h>
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#include <linux/compat.h>
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#include <power/regulator.h>
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#include <linux/iopoll.h>
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#include <usb/xhci.h>
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/* IPPC (IP Port Control) registers */
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#define IPPC_IP_PW_CTRL0 0x00
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#define CTRL0_IP_SW_RST BIT(0)
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#define IPPC_IP_PW_CTRL1 0x04
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#define CTRL1_IP_HOST_PDN BIT(0)
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#define IPPC_IP_PW_STS1 0x10
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#define STS1_IP_SLEEP_STS BIT(30)
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#define STS1_U3_MAC_RST BIT(16)
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#define STS1_XHCI_RST BIT(11)
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#define STS1_SYS125_RST BIT(10)
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#define STS1_REF_RST BIT(8)
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#define STS1_SYSPLL_STABLE BIT(0)
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#define IPPC_IP_XHCI_CAP 0x24
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#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
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#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
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#define IPPC_U3_CTRL_0P 0x30
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#define CTRL_U3_PORT_HOST_SEL BIT(2)
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#define CTRL_U3_PORT_PDN BIT(1)
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#define CTRL_U3_PORT_DIS BIT(0)
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#define IPPC_U2_CTRL_0P 0x50
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#define CTRL_U2_PORT_HOST_SEL BIT(2)
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#define CTRL_U2_PORT_PDN BIT(1)
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#define CTRL_U2_PORT_DIS BIT(0)
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#define IPPC_U3_CTRL(p) (IPPC_U3_CTRL_0P + ((p) * 0x08))
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#define IPPC_U2_CTRL(p) (IPPC_U2_CTRL_0P + ((p) * 0x08))
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struct mtk_xhci {
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struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
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struct xhci_hccr *hcd;
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void __iomem *ippc;
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struct udevice *dev;
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struct udevice *vusb33_supply;
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struct udevice *vbus_supply;
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struct clk_bulk clks;
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struct phy_bulk phys;
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int num_u2ports;
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int num_u3ports;
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};
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static int xhci_mtk_host_enable(struct mtk_xhci *mtk)
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{
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u32 value;
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u32 check_val;
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int ret;
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int i;
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/* power on host ip */
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clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
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/* power on and enable all u3 ports */
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for (i = 0; i < mtk->num_u3ports; i++) {
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clrsetbits_le32(mtk->ippc + IPPC_U3_CTRL(i),
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CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS,
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CTRL_U3_PORT_HOST_SEL);
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}
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/* power on and enable all u2 ports */
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for (i = 0; i < mtk->num_u2ports; i++) {
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clrsetbits_le32(mtk->ippc + IPPC_U2_CTRL(i),
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CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS,
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CTRL_U2_PORT_HOST_SEL);
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}
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/*
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* wait for clocks to be stable, and clock domains reset to
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* be inactive after power on and enable ports
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*/
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check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
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STS1_SYS125_RST | STS1_XHCI_RST;
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if (mtk->num_u3ports)
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check_val |= STS1_U3_MAC_RST;
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ret = readl_poll_timeout(mtk->ippc + IPPC_IP_PW_STS1, value,
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(check_val == (value & check_val)), 20000);
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if (ret)
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dev_err(mtk->dev, "clocks are not stable 0x%x!\n", value);
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return ret;
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}
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static int xhci_mtk_host_disable(struct mtk_xhci *mtk)
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{
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int i;
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/* power down all u3 ports */
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for (i = 0; i < mtk->num_u3ports; i++)
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setbits_le32(mtk->ippc + IPPC_U3_CTRL(i), CTRL_U3_PORT_PDN);
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/* power down all u2 ports */
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for (i = 0; i < mtk->num_u2ports; i++)
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setbits_le32(mtk->ippc + IPPC_U2_CTRL(i), CTRL_U2_PORT_PDN);
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/* power down host ip */
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setbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
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return 0;
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}
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static int xhci_mtk_ssusb_init(struct mtk_xhci *mtk)
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{
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u32 value;
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/* reset whole ip */
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setbits_le32(mtk->ippc + IPPC_IP_PW_CTRL0, CTRL0_IP_SW_RST);
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udelay(1);
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clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL0, CTRL0_IP_SW_RST);
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value = readl(mtk->ippc + IPPC_IP_XHCI_CAP);
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mtk->num_u3ports = CAP_U3_PORT_NUM(value);
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mtk->num_u2ports = CAP_U2_PORT_NUM(value);
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dev_info(mtk->dev, "u2p:%d, u3p:%d\n",
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mtk->num_u2ports, mtk->num_u3ports);
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return xhci_mtk_host_enable(mtk);
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}
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static int xhci_mtk_ofdata_get(struct mtk_xhci *mtk)
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{
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struct udevice *dev = mtk->dev;
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int ret = 0;
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mtk->hcd = devfdt_remap_addr_name(dev, "mac");
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if (!mtk->hcd) {
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dev_err(dev, "failed to get xHCI base address\n");
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return -ENXIO;
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}
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mtk->ippc = devfdt_remap_addr_name(dev, "ippc");
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if (!mtk->ippc) {
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dev_err(dev, "failed to get IPPC base address\n");
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return -ENXIO;
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}
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dev_info(dev, "hcd: 0x%p, ippc: 0x%p\n", mtk->hcd, mtk->ippc);
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ret = clk_get_bulk(dev, &mtk->clks);
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if (ret) {
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dev_err(dev, "failed to get clocks %d!\n", ret);
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return ret;
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}
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ret = device_get_supply_regulator(dev, "vusb33-supply",
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&mtk->vusb33_supply);
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if (ret)
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debug("can't get vusb33 regulator %d!\n", ret);
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ret = device_get_supply_regulator(dev, "vbus-supply",
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&mtk->vbus_supply);
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if (ret)
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debug("can't get vbus regulator %d!\n", ret);
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return 0;
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}
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static int xhci_mtk_ldos_enable(struct mtk_xhci *mtk)
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{
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int ret;
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ret = regulator_set_enable(mtk->vusb33_supply, true);
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if (ret < 0 && ret != -ENOSYS) {
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dev_err(mtk->dev, "failed to enable vusb33 %d!\n", ret);
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return ret;
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}
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ret = regulator_set_enable(mtk->vbus_supply, true);
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if (ret < 0 && ret != -ENOSYS) {
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dev_err(mtk->dev, "failed to enable vbus %d!\n", ret);
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regulator_set_enable(mtk->vusb33_supply, false);
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return ret;
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}
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return 0;
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}
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static void xhci_mtk_ldos_disable(struct mtk_xhci *mtk)
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{
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regulator_set_enable(mtk->vbus_supply, false);
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regulator_set_enable(mtk->vusb33_supply, false);
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}
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static int xhci_mtk_phy_setup(struct mtk_xhci *mtk)
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{
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struct udevice *dev = mtk->dev;
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struct phy_bulk *phys = &mtk->phys;
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int ret;
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ret = generic_phy_get_bulk(dev, phys);
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if (ret)
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return ret;
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ret = generic_phy_init_bulk(phys);
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if (ret)
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return ret;
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ret = generic_phy_power_on_bulk(phys);
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if (ret)
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generic_phy_exit_bulk(phys);
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return ret;
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}
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static void xhci_mtk_phy_shutdown(struct mtk_xhci *mtk)
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{
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generic_phy_power_off_bulk(&mtk->phys);
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generic_phy_exit_bulk(&mtk->phys);
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}
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static int xhci_mtk_probe(struct udevice *dev)
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{
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struct mtk_xhci *mtk = dev_get_priv(dev);
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struct xhci_hcor *hcor;
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int ret;
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mtk->dev = dev;
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ret = xhci_mtk_ofdata_get(mtk);
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if (ret)
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return ret;
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ret = xhci_mtk_ldos_enable(mtk);
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if (ret)
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goto ldos_err;
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ret = clk_enable_bulk(&mtk->clks);
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if (ret)
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goto clks_err;
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ret = xhci_mtk_phy_setup(mtk);
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if (ret)
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goto phys_err;
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ret = xhci_mtk_ssusb_init(mtk);
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if (ret)
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goto ssusb_init_err;
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hcor = (struct xhci_hcor *)((uintptr_t)mtk->hcd +
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HC_LENGTH(xhci_readl(&mtk->hcd->cr_capbase)));
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return xhci_register(dev, mtk->hcd, hcor);
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ssusb_init_err:
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xhci_mtk_phy_shutdown(mtk);
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phys_err:
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clk_disable_bulk(&mtk->clks);
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clks_err:
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xhci_mtk_ldos_disable(mtk);
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ldos_err:
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return ret;
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}
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static int xhci_mtk_remove(struct udevice *dev)
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{
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struct mtk_xhci *mtk = dev_get_priv(dev);
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xhci_deregister(dev);
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xhci_mtk_host_disable(mtk);
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xhci_mtk_ldos_disable(mtk);
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clk_disable_bulk(&mtk->clks);
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return 0;
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}
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static const struct udevice_id xhci_mtk_ids[] = {
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{ .compatible = "mediatek,mtk-xhci" },
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{ }
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};
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U_BOOT_DRIVER(usb_xhci) = {
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.name = "xhci-mtk",
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.id = UCLASS_USB,
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.of_match = xhci_mtk_ids,
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.probe = xhci_mtk_probe,
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.remove = xhci_mtk_remove,
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.ops = &xhci_usb_ops,
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.bind = dm_scan_fdt_dev,
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.priv_auto_alloc_size = sizeof(struct mtk_xhci),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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