100 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			100 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
| /*
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|  * Copyright 2008 Extreme Engineering Solutions, Inc.
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|  *
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|  * See file CREDITS for list of people who contributed to this
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|  * project.
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License as
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|  * published by the Free Software Foundation; either version 2 of
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|  * the License, or (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, write to the Free Software
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|  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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|  * MA 02111-1307 USA
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|  */
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| 
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| #include <common.h>
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| #include <asm/fsl_ddr_sdram.h>
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| #include <asm/mmu.h>
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| 
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| #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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| extern void ddr_enable_ecc(unsigned int dram_size);
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| #endif
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| 
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| phys_size_t initdram(int board_type)
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| {
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| 	phys_size_t dram_size = fsl_ddr_sdram();
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| 
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| #ifdef CONFIG_MPC85xx
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| 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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| 	dram_size *= 0x100000;
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| #endif
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| 
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| #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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| 	/* Initialize and enable DDR ECC */
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| 	ddr_enable_ecc(dram_size);
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| #endif
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| 
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| 	return dram_size;
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| }
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| 
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| #if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1)
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| void board_add_ram_info(int use_default)
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| {
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| #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
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| #if defined(CONFIG_MPC85xx)
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| 	volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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| #elif defined(CONFIG_MPC86xx)
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| 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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| 	volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
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| #endif
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| #endif
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| 
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| 	puts(" (");
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| 
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| #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
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| 	/* Print interleaving information */
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| 	if (ddr1->cs0_config & 0x20000000) {
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| 		switch ((ddr1->cs0_config >> 24) & 0xf) {
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| 		case 0:
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| 			puts("cache line");
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| 			break;
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| 		case 1:
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| 			puts("page");
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| 			break;
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| 		case 2:
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| 			puts("bank");
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| 			break;
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| 		case 3:
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| 			puts("super-bank");
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| 			break;
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| 		default:
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| 			puts("invalid");
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| 			break;
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| 		}
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| 	} else {
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| 		puts("no");
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| 	}
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| 
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| 	puts(" interleaving");
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| #endif
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| 
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| #if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC)
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| 	puts(", ");
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| #endif
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| 
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| #if defined(CONFIG_DDR_ECC)
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| 	puts("ECC enabled");
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| #endif
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| 
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| 	puts(")");
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| }
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| #endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */
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