465 lines
15 KiB
C
465 lines
15 KiB
C
/******************************************************************************
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
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* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
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* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
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* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE.
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*
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* (C) Copyright 2007-2008 Michal Simek
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* Michal SIMEK <monstr@monstr.eu>
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*
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* (c) Copyright 2003 Xilinx Inc.
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* All rights reserved.
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*
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******************************************************************************/
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#include <config.h>
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#include <common.h>
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#include <net.h>
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#include <asm/io.h>
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#include <asm/asm.h>
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#undef DEBUG
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typedef struct {
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u32 regbaseaddress; /* Base address of registers */
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u32 databaseaddress; /* Base address of data for FIFOs */
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} xpacketfifov100b;
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typedef struct {
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u32 baseaddress; /* Base address (of IPIF) */
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u32 isstarted; /* Device is currently started 0-no, 1-yes */
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xpacketfifov100b recvfifo; /* FIFO used to receive frames */
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xpacketfifov100b sendfifo; /* FIFO used to send frames */
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} xemac;
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#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
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#define XIIF_V123B_RESET_MASK 0xAUL
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#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
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/* This constant is used with the Reset Register */
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#define XPF_RESET_FIFO_MASK 0x0000000A
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#define XPF_COUNT_STATUS_REG_OFFSET 4UL
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/* These constants are used with the Occupancy/Vacancy Count Register. This
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* register also contains FIFO status */
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#define XPF_COUNT_MASK 0x0000FFFF
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#define XPF_DEADLOCK_MASK 0x20000000
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/* Offset of the MAC registers from the IPIF base address */
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#define XEM_REG_OFFSET 0x1100UL
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/*
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* Register offsets for the Ethernet MAC. Each register is 32 bits.
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*/
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#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */
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#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */
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#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */
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#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */
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#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */
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#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */
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#define XEM_PFIFO_OFFSET 0x2000UL
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/* Tx registers */
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#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0)
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/* Rx registers */
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#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10)
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/* Tx keyhole */
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#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100)
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/* Rx keyhole */
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#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200)
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/*
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* EMAC Interrupt Registers (Status and Enable) masks. These registers are
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* part of the IPIF IP Interrupt registers
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*/
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/* A mask for all transmit interrupts, used in polled mode */
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#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\
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XEM_EIR_XMIT_ERROR_MASK | \
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XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\
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XEM_EIR_XMIT_LFIFO_FULL_MASK)
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/* Xmit complete */
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#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL
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/* Recv complete */
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#define XEM_EIR_RECV_DONE_MASK 0x00000002UL
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/* Xmit error */
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#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL
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/* Recv error */
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#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL
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/* Xmit status fifo empty */
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#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL
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/* Recv length fifo empty */
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#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL
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/* Xmit length fifo full */
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#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL
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/* Recv length fifo overrun */
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#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL
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/* Recv length fifo underrun */
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#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL
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/* Xmit status fifo overrun */
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#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL
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/* Transmit status fifo underrun */
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#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL
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/* Transmit length fifo overrun */
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#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL
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/* Transmit length fifo underrun */
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#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL
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/* Transmit pause pkt received */
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#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL
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/*
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* EMAC Control Register (ECR)
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*/
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/* Full duplex mode */
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#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL
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/* Reset transmitter */
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#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL
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/* Enable transmitter */
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#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL
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/* Reset receiver */
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#define XEM_ECR_RECV_RESET_MASK 0x10000000UL
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/* Enable receiver */
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#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL
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/* Enable PHY */
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#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL
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/* Enable xmit pad insert */
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#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL
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/* Enable xmit FCS insert */
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#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL
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/* Enable unicast addr */
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#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL
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/* Enable broadcast addr */
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#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL
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/*
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* Transmit Status Register (TSR)
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*/
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/* Transmit excess deferral */
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#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL
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/* Transmit late collision */
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#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL
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#define ENET_MAX_MTU PKTSIZE
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#define ENET_ADDR_LENGTH 6
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static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
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static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
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static xemac emac;
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void eth_halt(void)
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{
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debug ("eth_halt\n");
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}
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int eth_init(bd_t * bis)
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{
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uchar enetaddr[6];
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u32 helpreg;
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debug ("EMAC Initialization Started\n\r");
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if (emac.isstarted) {
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puts("Emac is started\n");
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return 0;
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}
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memset (&emac, 0, sizeof (xemac));
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emac.baseaddress = XILINX_EMAC_BASEADDR;
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/* Setting up FIFOs */
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emac.recvfifo.regbaseaddress = emac.baseaddress +
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XEM_PFIFO_RXREG_OFFSET;
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emac.recvfifo.databaseaddress = emac.baseaddress +
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XEM_PFIFO_RXDATA_OFFSET;
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out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
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emac.sendfifo.regbaseaddress = emac.baseaddress +
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XEM_PFIFO_TXREG_OFFSET;
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emac.sendfifo.databaseaddress = emac.baseaddress +
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XEM_PFIFO_TXDATA_OFFSET;
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out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
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/* Reset the entire IPIF */
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out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET,
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XIIF_V123B_RESET_MASK);
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/* Stopping EMAC for setting up MAC */
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helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
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helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
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out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
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if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
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memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH);
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eth_setenv_enetaddr("ethaddr", enetaddr);
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}
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/* Set the device station address high and low registers */
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helpreg = (enetaddr[0] << 8) | enetaddr[1];
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out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg);
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helpreg = (enetaddr[2] << 24) | (enetaddr[3] << 16) |
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(enetaddr[4] << 8) | enetaddr[5];
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out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg);
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helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
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XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK |
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XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK;
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out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
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emac.isstarted = 1;
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/* Enable the transmitter, and receiver */
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helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
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helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
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helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
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out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
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printf("EMAC Initialization complete\n\r");
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return 0;
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}
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int eth_send(volatile void *ptr, int len)
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{
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u32 intrstatus;
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u32 xmitstatus;
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u32 fifocount;
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u32 wordcount;
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u32 extrabytecount;
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u32 *wordbuffer = (u32 *) ptr;
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if (len > ENET_MAX_MTU)
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len = ENET_MAX_MTU;
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/*
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* Check for overruns and underruns for the transmit status and length
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* FIFOs and make sure the send packet FIFO is not deadlocked.
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* Any of these conditions is bad enough that we do not want to
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* continue. The upper layer software should reset the device to resolve
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* the error.
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*/
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intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
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if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
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XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
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debug ("Transmitting overrun error\n");
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return 0;
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} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
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XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
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debug ("Transmitting underrun error\n");
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return 0;
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} else if (in_be32 (emac.sendfifo.regbaseaddress +
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XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) {
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debug ("Transmitting fifo error\n");
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return 0;
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}
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/*
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* Before writing to the data FIFO, make sure the length FIFO is not
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* full. The data FIFO might not be full yet even though the length FIFO
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* is. This avoids an overrun condition on the length FIFO and keeps the
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* FIFOs in sync.
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*
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* Clear the latched LFIFO_FULL bit so next time around the most
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* current status is represented
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*/
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if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
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out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
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intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK);
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debug ("Fifo is full\n");
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return 0;
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}
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/* get the count of how many words may be inserted into the FIFO */
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fifocount = in_be32 (emac.sendfifo.regbaseaddress +
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XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
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wordcount = len >> 2;
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extrabytecount = len & 0x3;
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if (fifocount < wordcount) {
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debug ("Sending packet is larger then size of FIFO\n");
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return 0;
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}
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for (fifocount = 0; fifocount < wordcount; fifocount++) {
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out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]);
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}
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if (extrabytecount > 0) {
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u32 lastword = 0;
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u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount);
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if (extrabytecount == 1) {
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lastword = extrabytesbuffer[0] << 24;
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} else if (extrabytecount == 2) {
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lastword = extrabytesbuffer[0] << 24 |
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extrabytesbuffer[1] << 16;
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} else if (extrabytecount == 3) {
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lastword = extrabytesbuffer[0] << 24 |
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extrabytesbuffer[1] << 16 |
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extrabytesbuffer[2] << 8;
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}
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out_be32 (emac.sendfifo.databaseaddress, lastword);
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}
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/* Loop on the MAC's status to wait for any pause to complete */
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intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
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while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
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intrstatus = in_be32 ((emac.baseaddress) +
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XIIF_V123B_IISR_OFFSET);
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/* Clear the pause status from the transmit status register */
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out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
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intrstatus & XEM_EIR_XMIT_PAUSE_MASK);
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}
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/*
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* Set the MAC's transmit packet length register to tell it to transmit
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*/
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out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len);
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/*
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* Loop on the MAC's status to wait for the transmit to complete.
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* The transmit status is in the FIFO when the XMIT_DONE bit is set.
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*/
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do {
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intrstatus = in_be32 ((emac.baseaddress) +
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XIIF_V123B_IISR_OFFSET);
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}
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while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0);
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xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET);
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if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
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XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
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debug ("Transmitting overrun error\n");
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return 0;
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} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
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XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
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debug ("Transmitting underrun error\n");
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return 0;
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}
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/* Clear the interrupt status register of transmit statuses */
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out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
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intrstatus & XEM_EIR_XMIT_ALL_MASK);
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/*
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* Collision errors are stored in the transmit status register
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* instead of the interrupt status register
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*/
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if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
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(xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) {
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debug ("Transmitting collision error\n");
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return 0;
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}
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return 1;
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}
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int eth_rx(void)
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{
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u32 pktlength;
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u32 intrstatus;
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u32 fifocount;
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u32 wordcount;
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u32 extrabytecount;
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u32 lastword;
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u8 *extrabytesbuffer;
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if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET)
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& XPF_DEADLOCK_MASK) {
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out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
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debug ("Receiving FIFO deadlock\n");
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return 0;
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}
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/*
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* Get the interrupt status to know what happened (whether an error
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* occurred and/or whether frames have been received successfully).
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* When clearing the intr status register, clear only statuses that
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* pertain to receive.
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*/
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intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
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/*
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* Before reading from the length FIFO, make sure the length FIFO is not
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* empty. We could cause an underrun error if we try to read from an
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* empty FIFO.
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*/
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if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) {
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/* debug ("Receiving FIFO is empty\n"); */
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return 0;
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}
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/*
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* Determine, from the MAC, the length of the next packet available
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* in the data FIFO (there should be a non-zero length here)
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*/
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pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET);
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if (!pktlength) {
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return 0;
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}
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/*
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* Write the RECV_DONE bit in the status register to clear it. This bit
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* indicates the RPLR is non-empty, and we know it's set at this point.
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* We clear it so that subsequent entry into this routine will reflect
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* the current status. This is done because the non-empty bit is latched
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* in the IPIF, which means it may indicate a non-empty condition even
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* though there is something in the FIFO.
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*/
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out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
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XEM_EIR_RECV_DONE_MASK);
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fifocount = in_be32 (emac.recvfifo.regbaseaddress +
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XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
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if ((fifocount * 4) < pktlength) {
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debug ("Receiving FIFO is smaller than packet size.\n");
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return 0;
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}
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wordcount = pktlength >> 2;
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extrabytecount = pktlength & 0x3;
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for (fifocount = 0; fifocount < wordcount; fifocount++) {
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etherrxbuff[fifocount] =
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in_be32 (emac.recvfifo.databaseaddress);
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}
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/*
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* if there are extra bytes to handle, read the last word from the FIFO
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* and insert the extra bytes into the buffer
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*/
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if (extrabytecount > 0) {
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extrabytesbuffer = (u8 *) (etherrxbuff + wordcount);
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|
lastword = in_be32 (emac.recvfifo.databaseaddress);
|
|
|
|
/*
|
|
* one extra byte in the last word, put the byte into the next
|
|
* location of the buffer, bytes in a word of the FIFO are
|
|
* ordered from most significant byte to least
|
|
*/
|
|
if (extrabytecount == 1) {
|
|
extrabytesbuffer[0] = (u8) (lastword >> 24);
|
|
} else if (extrabytecount == 2) {
|
|
extrabytesbuffer[0] = (u8) (lastword >> 24);
|
|
extrabytesbuffer[1] = (u8) (lastword >> 16);
|
|
} else if (extrabytecount == 3) {
|
|
extrabytesbuffer[0] = (u8) (lastword >> 24);
|
|
extrabytesbuffer[1] = (u8) (lastword >> 16);
|
|
extrabytesbuffer[2] = (u8) (lastword >> 8);
|
|
}
|
|
}
|
|
NetReceive((uchar *)etherrxbuff, pktlength);
|
|
return 1;
|
|
}
|