166 lines
5.6 KiB
C
166 lines
5.6 KiB
C
/*
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* NS16550 Serial Port
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* originally from linux source (arch/ppc/boot/ns16550.h)
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*
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* Cleanup and unification
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* (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
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*
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* modified slightly to
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* have addresses as offsets from CONFIG_SYS_ISA_BASE
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* added a few more definitions
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* added prototypes for ns16550.c
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* reduced no of com ports to 2
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* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
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*
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* added support for port on 64-bit bus
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* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
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*/
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/*
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* Note that the following macro magic uses the fact that the compiler
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* will not allocate storage for arrays of size 0
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*/
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#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
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#error "Please define NS16550 registers size."
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#elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
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#define UART_REG(x) \
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unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
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unsigned char x;
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#elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
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#define UART_REG(x) \
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unsigned char x; \
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unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
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#endif
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struct NS16550 {
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UART_REG(rbr); /* 0 */
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UART_REG(ier); /* 1 */
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UART_REG(fcr); /* 2 */
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UART_REG(lcr); /* 3 */
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UART_REG(mcr); /* 4 */
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UART_REG(lsr); /* 5 */
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UART_REG(msr); /* 6 */
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UART_REG(spr); /* 7 */
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UART_REG(mdr1); /* 8 */
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UART_REG(reg9); /* 9 */
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UART_REG(regA); /* A */
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UART_REG(regB); /* B */
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UART_REG(regC); /* C */
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UART_REG(regD); /* D */
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UART_REG(regE); /* E */
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UART_REG(uasr); /* F */
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UART_REG(scr); /* 10*/
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UART_REG(ssr); /* 11*/
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UART_REG(reg12); /* 12*/
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UART_REG(osc_12m_sel); /* 13*/
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};
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#define thr rbr
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#define iir fcr
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#define dll rbr
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#define dlm ier
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typedef volatile struct NS16550 *NS16550_t;
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/*
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* These are the definitions for the FIFO Control Register
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*/
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#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
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#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
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#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
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#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
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#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
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#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
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#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
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#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_DTR 0x01 /* DTR */
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#define UART_MCR_RTS 0x02 /* RTS */
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#define UART_MCR_OUT1 0x04 /* Out 1 */
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#define UART_MCR_OUT2 0x08 /* Out 2 */
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_DMA_EN 0x04
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#define UART_MCR_TX_DFR 0x08
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/*
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* These are the definitions for the Line Control Register
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*
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* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
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* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
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*/
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#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
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#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
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#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
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#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
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#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
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#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
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#define UART_LCR_PEN 0x08 /* Parity eneble */
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#define UART_LCR_EPS 0x10 /* Even Parity Select */
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#define UART_LCR_STKP 0x20 /* Stick Parity */
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#define UART_LCR_SBRK 0x40 /* Set Break */
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#define UART_LCR_BKSE 0x80 /* Bank select enable */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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/*
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* These are the definitions for the Line Status Register
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*/
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#define UART_LSR_DR 0x01 /* Data ready */
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#define UART_LSR_OE 0x02 /* Overrun */
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#define UART_LSR_PE 0x04 /* Parity error */
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#define UART_LSR_FE 0x08 /* Framing error */
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#define UART_LSR_BI 0x10 /* Break */
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#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
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#define UART_LSR_TEMT 0x40 /* Xmitter empty */
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#define UART_LSR_ERR 0x80 /* Error */
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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/*
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* These are the definitions for the Interrupt Identification Register
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*/
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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/*
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* These are the definitions for the Interrupt Enable Register
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*/
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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#ifdef CONFIG_OMAP1510
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#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */
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#endif
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/* useful defaults for LCR */
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#define UART_LCR_8N1 0x03
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void NS16550_init (NS16550_t com_port, int baud_divisor);
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void NS16550_putc (NS16550_t com_port, char c);
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char NS16550_getc (NS16550_t com_port);
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int NS16550_tstc (NS16550_t com_port);
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void NS16550_reinit (NS16550_t com_port, int baud_divisor);
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