293 lines
10 KiB
C
293 lines
10 KiB
C
/*-
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* Copyright (c) 2007-2008, Juniper Networks, Inc.
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* Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
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* All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef USB_EHCI_H
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#define USB_EHCI_H
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#include <usb.h>
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/* Section 2.2.3 - N_PORTS */
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#define MAX_HC_PORTS 15
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/*
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* Register Space.
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*/
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struct ehci_hccr {
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uint32_t cr_capbase;
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#define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
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#define HC_VERSION(p) (((p) >> 16) & 0xffff)
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uint32_t cr_hcsparams;
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#define HCS_PPC(p) ((p) & (1 << 4))
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#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
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#define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
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uint32_t cr_hccparams;
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uint8_t cr_hcsp_portrt[8];
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} __attribute__ ((packed, aligned(4)));
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struct ehci_hcor {
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uint32_t or_usbcmd;
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#define CMD_PARK (1 << 11) /* enable "park" */
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#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
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#define CMD_LRESET (1 << 7) /* partial reset */
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#define CMD_IAAD (1 << 6) /* "doorbell" interrupt */
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#define CMD_ASE (1 << 5) /* async schedule enable */
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#define CMD_PSE (1 << 4) /* periodic schedule enable */
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#define CMD_RESET (1 << 1) /* reset HC not bus */
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#define CMD_RUN (1 << 0) /* start/stop HC */
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uint32_t or_usbsts;
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#define STS_ASS (1 << 15)
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#define STS_PSS (1 << 14)
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#define STS_HALT (1 << 12)
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uint32_t or_usbintr;
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#define INTR_UE (1 << 0) /* USB interrupt enable */
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#define INTR_UEE (1 << 1) /* USB error interrupt enable */
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#define INTR_PCE (1 << 2) /* Port change detect enable */
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#define INTR_SEE (1 << 4) /* system error enable */
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#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
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uint32_t or_frindex;
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uint32_t or_ctrldssegment;
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uint32_t or_periodiclistbase;
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uint32_t or_asynclistaddr;
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uint32_t _reserved_0_;
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uint32_t or_burstsize;
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uint32_t or_txfilltuning;
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#define TXFIFO_THRESH_MASK (0x3f << 16)
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#define TXFIFO_THRESH(p) ((p & 0x3f) << 16)
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uint32_t _reserved_1_[6];
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uint32_t or_configflag;
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#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
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uint32_t or_portsc[MAX_HC_PORTS];
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#define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
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#define PORTSC_PSPD_FS 0x0
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#define PORTSC_PSPD_LS 0x1
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#define PORTSC_PSPD_HS 0x2
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uint32_t or_systune;
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} __attribute__ ((packed, aligned(4)));
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#define USBMODE 0x68 /* USB Device mode */
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#define USBMODE_SDIS (1 << 3) /* Stream disable */
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#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
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#define USBMODE_CM_HC (3 << 0) /* host controller mode */
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#define USBMODE_CM_IDLE (0 << 0) /* idle state */
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/* Interface descriptor */
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struct usb_linux_interface_descriptor {
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unsigned char bLength;
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unsigned char bDescriptorType;
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unsigned char bInterfaceNumber;
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unsigned char bAlternateSetting;
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unsigned char bNumEndpoints;
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unsigned char bInterfaceClass;
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unsigned char bInterfaceSubClass;
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unsigned char bInterfaceProtocol;
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unsigned char iInterface;
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} __attribute__ ((packed));
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/* Configuration descriptor information.. */
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struct usb_linux_config_descriptor {
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unsigned char bLength;
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unsigned char bDescriptorType;
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unsigned short wTotalLength;
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unsigned char bNumInterfaces;
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unsigned char bConfigurationValue;
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unsigned char iConfiguration;
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unsigned char bmAttributes;
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unsigned char MaxPower;
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} __attribute__ ((packed));
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#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
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#define ehci_readl(x) be32_to_cpu(__raw_readl(x))
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#define ehci_writel(a, b) __raw_writel(cpu_to_be32(b), a)
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#else
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#define ehci_readl(x) readl(x)
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#define ehci_writel(a, b) writel(b, a)
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#endif
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#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
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#define hc32_to_cpu(x) be32_to_cpu((x))
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#define cpu_to_hc32(x) cpu_to_be32((x))
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#else
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#define hc32_to_cpu(x) le32_to_cpu((x))
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#define cpu_to_hc32(x) cpu_to_le32((x))
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#endif
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#define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
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#define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
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#define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
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#define EHCI_PS_PO (1 << 13) /* RW port owner */
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#define EHCI_PS_PP (1 << 12) /* RW,RO port power */
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#define EHCI_PS_LS (3 << 10) /* RO line status */
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#define EHCI_PS_PR (1 << 8) /* RW port reset */
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#define EHCI_PS_SUSP (1 << 7) /* RW suspend */
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#define EHCI_PS_FPR (1 << 6) /* RW force port resume */
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#define EHCI_PS_OCC (1 << 5) /* RWC over current change */
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#define EHCI_PS_OCA (1 << 4) /* RO over current active */
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#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
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#define EHCI_PS_PE (1 << 2) /* RW port enable */
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#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
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#define EHCI_PS_CS (1 << 0) /* RO connect status */
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#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
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#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
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/*
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* Schedule Interface Space.
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*
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* IMPORTANT: Software must ensure that no interface data structure
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* reachable by the EHCI host controller spans a 4K page boundary!
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*
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* Periodic transfers (i.e. isochronous and interrupt transfers) are
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* not supported.
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*/
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/* Queue Element Transfer Descriptor (qTD). */
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struct qTD {
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/* this part defined by EHCI spec */
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uint32_t qt_next; /* see EHCI 3.5.1 */
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#define QT_NEXT_TERMINATE 1
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uint32_t qt_altnext; /* see EHCI 3.5.2 */
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uint32_t qt_token; /* see EHCI 3.5.3 */
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#define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */
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#define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1)
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#define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */
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#define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff)
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#define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */
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#define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */
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#define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */
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#define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */
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#define QT_TOKEN_PID_OUT 0x0
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#define QT_TOKEN_PID_IN 0x1
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#define QT_TOKEN_PID_SETUP 0x2
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#define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */
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#define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff)
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#define QT_TOKEN_STATUS_ACTIVE 0x80
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#define QT_TOKEN_STATUS_HALTED 0x40
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#define QT_TOKEN_STATUS_DATBUFERR 0x20
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#define QT_TOKEN_STATUS_BABBLEDET 0x10
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#define QT_TOKEN_STATUS_XACTERR 0x08
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#define QT_TOKEN_STATUS_MISSEDUFRAME 0x04
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#define QT_TOKEN_STATUS_SPLITXSTATE 0x02
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#define QT_TOKEN_STATUS_PERR 0x01
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#define QT_BUFFER_CNT 5
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uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */
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uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */
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/* pad struct for 32 byte alignment */
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uint32_t unused[3];
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};
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#define EHCI_PAGE_SIZE 4096
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/* Queue Head (QH). */
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struct QH {
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uint32_t qh_link;
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#define QH_LINK_TERMINATE 1
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#define QH_LINK_TYPE_ITD 0
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#define QH_LINK_TYPE_QH 2
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#define QH_LINK_TYPE_SITD 4
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#define QH_LINK_TYPE_FSTN 6
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uint32_t qh_endpt1;
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#define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */
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#define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */
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#define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */
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#define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */
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#define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */
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#define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0
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#define QH_ENDPT1_DTC_DT_FROM_QTD 0x1
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#define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */
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#define QH_ENDPT1_EPS_FS 0x0
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#define QH_ENDPT1_EPS_LS 0x1
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#define QH_ENDPT1_EPS_HS 0x2
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#define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */
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#define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */
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#define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */
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uint32_t qh_endpt2;
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#define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */
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#define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */
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#define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */
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#define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */
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#define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */
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uint32_t qh_curtd;
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struct qTD qh_overlay;
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/*
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* Add dummy fill value to make the size of this struct
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* aligned to 32 bytes
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*/
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union {
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uint32_t fill[4];
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void *buffer;
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};
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};
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/* Tweak flags for EHCI, used to control operation */
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enum {
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/* don't use or_configflag in init */
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EHCI_TWEAK_NO_INIT_CF = 1 << 0,
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};
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struct ehci_ctrl;
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struct ehci_ops {
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void (*set_usb_mode)(struct ehci_ctrl *ctrl);
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int (*get_port_speed)(struct ehci_ctrl *ctrl, uint32_t reg);
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void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg,
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uint32_t *reg);
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uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port);
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int (*init_after_reset)(struct ehci_ctrl *ctrl);
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};
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struct ehci_ctrl {
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enum usb_init_type init;
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struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
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struct ehci_hcor *hcor;
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int rootdev;
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uint16_t portreset;
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struct QH qh_list __aligned(USB_DMA_MINALIGN);
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struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
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uint32_t *periodic_list;
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int periodic_schedules;
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int ntds;
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struct ehci_ops ops;
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void *priv; /* client's private data */
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};
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/**
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* ehci_set_controller_info() - Set up private data for the controller
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*
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* This function can be called in ehci_hcd_init() to tell the EHCI layer
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* about the controller's private data pointer. Then in the above functions
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* this can be accessed given the struct ehci_ctrl pointer. Also special
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* EHCI operation methods can be provided if required
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*
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* @index: Controller number to set
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* @priv: Controller pointer
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* @ops: Controller operations, or NULL to use default
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*/
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void ehci_set_controller_priv(int index, void *priv,
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const struct ehci_ops *ops);
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/**
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* ehci_get_controller_priv() - Get controller private data
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*
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* @index Controller number to get
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* @return controller pointer for this index
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*/
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void *ehci_get_controller_priv(int index);
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/* Low level init functions */
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor);
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int ehci_hcd_stop(int index);
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int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
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struct ehci_hcor *hcor, const struct ehci_ops *ops,
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uint tweaks, enum usb_init_type init);
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int ehci_deregister(struct udevice *dev);
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extern struct dm_usb_ops ehci_usb_ops;
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#endif /* USB_EHCI_H */
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