66 lines
2.2 KiB
C
66 lines
2.2 KiB
C
/*
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* Copyright 2014, Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
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#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
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#include <fsl_ddrc_version.h>
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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#define CONFIG_SYS_IMMR 0x01000000
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#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
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#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
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#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
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#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
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#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
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#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
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#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
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#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
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#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
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#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
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0x18A0)
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#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
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#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
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#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
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#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06100000
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/* SMMU Defintions */
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#define SMMU_BASE 0x05000000 /* GR0 Base */
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/* DDR */
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#define CONFIG_SYS_FSL_DDR_LE
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
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#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
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#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
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/* IFC */
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#define CONFIG_SYS_FSL_IFC_LE
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#ifdef CONFIG_LS2085A
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#define CONFIG_MAX_CPUS 16
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_NUM_DDR_CONTROLLERS 2
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
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#else
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#error SoC not defined
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#endif
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#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
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