157 lines
4.3 KiB
C
157 lines
4.3 KiB
C
/*
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* Keystone2: Common SoC definitions, structures etc.
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <config.h>
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#ifndef __ASSEMBLY__
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#include <linux/sizes.h>
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#include <asm/io.h>
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#define REG(addr) (*(volatile unsigned int *)(addr))
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#define REG_P(addr) ((volatile unsigned int *)(addr))
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typedef volatile unsigned int dv_reg;
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typedef volatile unsigned int *dv_reg_p;
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struct ddr3_phy_config {
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unsigned int pllcr;
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unsigned int pgcr1_mask;
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unsigned int pgcr1_val;
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unsigned int ptr0;
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unsigned int ptr1;
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unsigned int ptr2;
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unsigned int ptr3;
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unsigned int ptr4;
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unsigned int dcr_mask;
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unsigned int dcr_val;
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unsigned int dtpr0;
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unsigned int dtpr1;
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unsigned int dtpr2;
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unsigned int mr0;
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unsigned int mr1;
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unsigned int mr2;
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unsigned int dtcr;
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unsigned int pgcr2;
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unsigned int zq0cr1;
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unsigned int zq1cr1;
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unsigned int zq2cr1;
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unsigned int pir_v1;
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unsigned int pir_v2;
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};
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struct ddr3_emif_config {
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unsigned int sdcfg;
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unsigned int sdtim1;
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unsigned int sdtim2;
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unsigned int sdtim3;
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unsigned int sdtim4;
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unsigned int zqcfg;
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unsigned int sdrfc;
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};
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#endif
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#define BIT(x) (1 << (x))
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#define KS2_DDRPHY_PIR_OFFSET 0x04
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#define KS2_DDRPHY_PGCR0_OFFSET 0x08
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#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
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#define KS2_DDRPHY_PGSR0_OFFSET 0x10
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#define KS2_DDRPHY_PGSR1_OFFSET 0x14
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#define KS2_DDRPHY_PLLCR_OFFSET 0x18
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#define KS2_DDRPHY_PTR0_OFFSET 0x1C
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#define KS2_DDRPHY_PTR1_OFFSET 0x20
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#define KS2_DDRPHY_PTR2_OFFSET 0x24
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#define KS2_DDRPHY_PTR3_OFFSET 0x28
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#define KS2_DDRPHY_PTR4_OFFSET 0x2C
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#define KS2_DDRPHY_DCR_OFFSET 0x44
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#define KS2_DDRPHY_DTPR0_OFFSET 0x48
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#define KS2_DDRPHY_DTPR1_OFFSET 0x4C
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#define KS2_DDRPHY_DTPR2_OFFSET 0x50
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#define KS2_DDRPHY_MR0_OFFSET 0x54
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#define KS2_DDRPHY_MR1_OFFSET 0x58
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#define KS2_DDRPHY_MR2_OFFSET 0x5C
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#define KS2_DDRPHY_DTCR_OFFSET 0x68
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#define KS2_DDRPHY_PGCR2_OFFSET 0x8C
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#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
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#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
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#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
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#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
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#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
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#define IODDRM_MASK 0x00000180
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#define ZCKSEL_MASK 0x01800000
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#define CL_MASK 0x00000072
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#define WR_MASK 0x00000E00
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#define BL_MASK 0x00000003
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#define RRMODE_MASK 0x00040000
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#define UDIMM_MASK 0x20000000
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#define BYTEMASK_MASK 0x0003FC00
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#define MPRDQ_MASK 0x00000080
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#define PDQ_MASK 0x00000070
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#define NOSRA_MASK 0x08000000
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#define ECC_MASK 0x00000001
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#define KS2_DDR3_MIDR_OFFSET 0x00
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#define KS2_DDR3_STATUS_OFFSET 0x04
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#define KS2_DDR3_SDCFG_OFFSET 0x08
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#define KS2_DDR3_SDRFC_OFFSET 0x10
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#define KS2_DDR3_SDTIM1_OFFSET 0x18
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#define KS2_DDR3_SDTIM2_OFFSET 0x1C
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#define KS2_DDR3_SDTIM3_OFFSET 0x20
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#define KS2_DDR3_SDTIM4_OFFSET 0x28
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#define KS2_DDR3_PMCTL_OFFSET 0x38
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#define KS2_DDR3_ZQCFG_OFFSET 0xC8
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#define KS2_UART0_BASE 0x02530c00
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#define KS2_UART1_BASE 0x02531000
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/* AEMIF */
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#define KS2_AEMIF_CNTRL_BASE 0x21000a00
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
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#ifdef CONFIG_SOC_K2HK
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#include <asm/arch/hardware-k2hk.h>
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#endif
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#ifndef __ASSEMBLY__
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static inline int cpu_is_k2hk(void)
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{
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unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
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unsigned int part_no = (jtag_id >> 12) & 0xffff;
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return (part_no == 0xb981) ? 1 : 0;
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}
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static inline int cpu_revision(void)
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{
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unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
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unsigned int rev = (jtag_id >> 28) & 0xf;
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return rev;
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}
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void share_all_segments(int priv_id);
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int cpu_to_bus(u32 *ptr, u32 length);
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void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
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void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
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void init_ddr3(void);
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void sdelay(unsigned long);
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#endif
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#endif /* __ASM_ARCH_HARDWARE_H */
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